MC9328MX21_10 Datasheet, PDF (38/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Specifications
Host Command
N_CR cycles
CMD S T Content CRC E Z Z P ****** P S T
Response
Content CRC E Z Z Z
Command response timing (data transfer mode)
CMD S T
Response
N_RC cycles
Host Command
Content CRC E Z
******
Z S T Content CRC E Z Z Z
Timing response end to next CMD start (data transfer mode)
Host Command
N_CC cycles
Host Command
CMD S T Content CRC E Z
******
Z S T Content CRC E Z Z Z
Timing of command sequences (all modes)
Figure 27. Timing Diagrams at Data Transfer Mode
Figure 28 shows basic read operation timing. In a read operation, the sequence starts with a single block
read command (which specifies the start address in the argument field). The response is sent on the
SD_CMD lines as usual. Data transmission from the card starts after the access time delay N_AC , beginning
from the last bit of the read command. If the system is in multiple block read mode, the card sends a
continuous flow of data blocks with distance N_AC until the card sees a stop transmission command. The
data stops two clock cycles after the end bit of the stop command.
MC9328MX21 Technical Data, Rev. 3.4
38
Freescale Semiconductor