MC9328MX21_10 Datasheet, PDF (24/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Specifications
1T
BMI_CLK/CS
BMI_READ_REQ
BMI_D[15:0]
Tdh
Tds
TxD1 TxD2
Trh
Last TxD
BMI_WRITE
DMA or CPU write data to TxFIFO
Figure 8. BMI Drives Clock, MMD Read BMI Timing
(MASTER_MODE_SEL=0, MMD_MODE_SEL=1, MMD_CLKOUT=1)
Table 16. MMD Read BMI Timing Table when BMI Drives Clock
Item
Transfer data setup time
Transfer data hold time
Read_req hold time
Symbol
Minimum
Typical
Maximum
Unit
Tds
2
Tdh
2
Trh
2
–
8
ns
–
8
ns
–
18
ns
Note: In this mode, the max frequency of the BMI_CLK/CS can be up to 36MHz (double as max data pad speed).
Note: The BMI_CLK/CS can only be divided by 2,4,8,16 from HCLK.
3.8.1.4 MMD Write BMI Timing
Figure 9 shows the MMD write BMI timing when BMI drives BMI_CLK/CS.
When the BMI_WRITE signal is asserted, the BMI can write a 1 to READ bit of control register to issue
a WRITE cycle. This bit is cleared automatically when the WRITE operation is completed. In a WRITE
burst the MMD will write COUNT+1 data to the BMI. The user can issue another WRITE operation if the
MMD still has data to write after the first operation completed.
The BMI can latch the data either at falling edge or the next rising edge of the BMI_CLK/CS according to
the DATA_LATCH bit. When the DATA_LATCH bit is set, the BMI latch data at the next rising edge and
latch the last data using the internal clock.
BMI_WRITE signal can not be negated when the WRITE operation is proceeding.
MC9328MX21 Technical Data, Rev. 3.4
24
Freescale Semiconductor