MC9328MX21_10 Datasheet, PDF (25/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Total has COUNT+1 clocks in one burst
Specifications
BMI_CLK/CS
BMI_READ_REQ
Can be asserted any time
Can be asserted any time
BMI_D[15:0]
BMI_WRITE
RxD1
Tds1
RxD2
Tds2
Last RxD
A 1 is written to READ bit of control register
Figure 9. BMI Drives Clock, MMD Write BMI Timing
(MASTER_MODE_SEL=0, MMD_MODE_SEL=1, MMD_CLKOUT=1)
Table 17. MMD Write BMI Timing Table when BMI Drives Clock
Item
Receive data setup time1
Receive data setup time2
Symbol
Minimum
Typical
Maximum
Unit
Tds1
14
–
Tds2
14
–
–
ns
–
ns
Note: The BMI_CLK/CS can only be up to 30MHz if BMI latch data at the falling edge and can be up to 36MHz (double as max
data pad speed) if BMI latch data at the next rising edge.
Note: Tds1 is the receive data setup time when BMI latch data at the falling edge.
Note: Tds2 is the receive data setup time when BMI latch data at the next rising edge.
3.8.2 Connecting BMI to External Bus Master Devices
In this mode both MASTER_SEL bit and MMD_MODE_SEL bit are cleared and the MMD_CLKOUT
bit is no useful. BMI_WRITE and BMI_CLK/CS are input signals driving by the external bus master. The
Output signal BMI_READ_REQ can be used as an interrupt signal to inform external bus master that data
is ready in the BMI TxFIFO for a read access. The external bus master can write data to the BMI RxFIFO
anytime since the CPU or DMA can move data out from RxFIFO much faster than the BMI interface. An
overflow interrupt is generated if RxFIFO overflow is detected. Once this happens, the new coming data
is ignored.
Each falling edge of BMI_CLK/CS will determine if the current cycle is read or write cycle. It drives data
and enables data out if BMI_WRITE is logic high. The D_EN signal remains active only while BMI_CLK/
CS is logic low and BMI_WRITE is logic high.
Each rising edge of BMI_CLK/CS will determine if data should be latched to RxFIFO from the data bus.
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
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