MC9328MX21_10 Datasheet, PDF (11/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
TIN
TOUT1
(or simply TOUT)
TOUT2
TOUT3
USB_BYP
USB_PWR
USB_OC
USBG_RXDP
USBG_RXDM
USBG_TXDP
USBG_TXDM
USBG_RXDAT
USBG_OE
USBG_ON
USBG_FS
USBH1_RXDP
USBH1_RXDM
USBH1_TXDP
USBH1_TXDM
USBH1_RXDAT
USBH1_OE
USBH1_FS
USBH_ON
USBH2_RXDP
USBH2_RXDM
USBH2_TXDP
USBH2_TXDM
USBH2_OE
Function/Notes
General Purpose Timers
Timer Input Capture or Timer Input Clock—The signal on this input is applied to all 3 timers
simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL, Clock, and
Reset Controller module.
Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with SYS_CLK1
and SYS_CLK2 signal of SSI1 and SSI2. The pin name of this signal is simply TOUT.
Timer Output signal from General Purpose Timer1 (GPT2). This signal is multiplexed with PWMO.
Timer Output signal from General Purpose Timer1 (GPT3). This signal is multiplexed with PWMO.
USB On-The-Go
USB Bypass input active low signal. This signal can only be used for USB function, not for GPIO.
USB Power output signal
USB Over current input signal. This signal can only be used for USB function, not for GPIO.
USB OTG Receive Data Plus input signal. This signal is muxed with SLCDC1_DAT15.
USB OTG Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT14.
USB OTG Transmit Data Plus output signal. This signal is muxed with SLCDC1_DAT13.
USB OTG Transmit Data Minus output signal. This signal is muxed with SLCDC1_DAT12.
USB OTG Transceiver differential data receive signal. Multiplexed with CSPI1_SS2.
USB OTG Output Enable signal. This signal is muxed with SLCDC1_DAT11.
USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9.
USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT
signal of USB OTG. This signal is muxed with SLCDC1_DAT10.
USB Host1 Receive Data Plus input signal. This signal is multiplexed with UART4_RXD and
SLCDC1_DAT6. It also provides an alternative multiplex for UART4_RTS, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USB Host1 Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT5. It also provides
an alternative multiplex for UART4_CTS.
USB Host1 Transmit Data Plus output signal. This signal is multiplexed with UART4_CTS and
SLCDC1_DAT4. It also provides an alternative multiplex for UART4_RXD, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USB Host1 Transmit Data Minus output signal. Multiplexed with UART4_TXD and SLCDC1_DAT3.
USB Host1 Transceiver differential data receive signal. Multiplexed with USBH1_FS.
USB Host1 Output Enable signal. This signal is muxed with SLCDC1_DAT2.
USB Host1 Full Speed output signal. Multiplexed with UART4_RTS and SLCDC1_DAT1 and
USBH1_RXDAT.
USB Host transceiver ON output signal. This signal is muxed with SLCDC1_DAT0.
USB Host2 Receive Data Plus input signal. This signal is multiplexed with CSPI2_SS[1] of CSPI2.
USB Host2 Receive Data Minus input signal. This signal is multiplexed with CSPI2_SS[2] of CSPI2.
USB Host2 Transmit Data Plus output signal. This signal is multiplexed with CSPI2_MOSI of CSPI2.
USB Host2 Transmit Data Minus output signal. This signal is multiplexed with CSPI2_MISO of CSPI2.
USB Host2 Output Enable signal. This signal is multiplexed with CSPI2_SCLK of CSPI2.
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
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