PXD20 Datasheet, PDF (61/130 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

System design information
Figure 7. Power-down sequencing
2. All 3.3V supplies (VDDE_B and VDD33_DR) should be ramped up first, and then the rest of the I/O supplies should
be ramped up (VDDA, VDDE_A, VDDM, and VDD_DR).
3. VDDR, the regulator input supply, should be the last supply to ramp up; all supplies can be ramped up together as long
as VDDR is included. So all 5V supplies should be ramped up after the 3.3 V supplies, and if all the supplies are of
the same level, they can be ramped up together as well.
4. LV supply (VDD12). If Vreg is in bypass mode and the core supply (1.2 V) is supplied externally, then this should be
the last supply given.
NOTE
For DDR, the 3.3 V supply (VDD33_DR) should come before VDD_DR.
This sequence ensures that when VREG releases its LVDs, the IO and other HV segments
are powered properly. This is important because PXD20 doesn't monitor LVDs on IO HV
supplies.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
61