PXD20 Datasheet, PDF (102/130 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Electrical characteristics
4.18 AC timing
4.18.1 IEEE 1149.1 interface timing
Table 52. JTAG interface timing¹
Num
Symbol
C
Characteristic
Min
Max Unit SpecID
1
t_JCYC
CC² D TCK Cycle Time
100
—
ns
A1.1
2
t_JDC
CC² D TCK Clock Pulse Width (Measured at V_DD/2)
40
60
ns
A1.2
3
t_TCKRISE CC² D TCK Rise and Fall Times (40% – 70%)
—
3
ns
A1.3
4 t_TMSS, t_TDIS CC² D TMS, TDI Data Setup Time
5
—
ns
A1.4
5 t_TMSH, t_TDIH CC² D TMS, TDI Data Hold Time
25
—
ns
A1.5
6
t_TDOV
CC² D TCK Low to TDO Data Valid
—
35
ns
A1.6
7
t_TDOI
CC² D TCK Low to TDO Data Invalid
0
—
ns
A1.7
8
t_TDOHZ CC² D TCK Low to TDO High Impedance
—
30
ns
A1.8
9
t_BSDV
CC² D TCK Falling Edge to Output Valid
—
35
ns
A1.9
10
t_BSDVZ
CC² D TCK Falling Edge to Output Valid out of High
—
50
ns
A1.10
Impedance
11
t_BSDHZ CC² D TCK Falling Edge to Output High Impedance
—
50
ns
A1.11
12
t_BSDST
CC² D Boundary Scan Input Valid to TCK Rising Edge
50
—
ns
A1.12
13
t_BSDHT CC² D TCK Rising Edge to Boundary Scan Input Invalid 50
—
ns
A1.13
1 _{These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 3.0 V to 3.6 V, TA = –40 to 105 °C,}
and CL = 50 pF with SRC = 0b01.
2 _{Parameter values guaranteed by design.}
TCK
3
2
2
1
3
Figure 18. JTAG test clock input timing
PXD20 Microcontroller Data Sheet, Rev. 2
102
Preliminary—Subject to Change Without Notice
Freescale Semiconductor