PXD20 Datasheet, PDF (12/130 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Overview
• Direct readback of the pin value supported on all digital output pins through the SIU
• Configurable digital input filter that can be applied to up to 24 general purpose input pins for noise elimination on
external interrupts
• Register configuration protected against change with soft lock for temporary guard or hard lock to prevent
modification until next reset.
1.4.8 On-chip flash memory with ECC
The PXD20 microcontroller has the following flash memory features:
• 2 MB of flash memory
— Typical flash memory access time: 0 wait-state for buffer hits, 3 wait-states for page buffer miss at 125 MHz
— Two 4 × 128-bit page buffers with programmable prefetch control
– One set of page buffers can be allocated for code-only, fixed partitions of code and data, all available for any
access
– One set of page buffers allocated to Display Controller Units, Graphics Accelerator and the eDMA
— 64-bit ECC with single-bit correction, double-bit detection for data integrity
• Small block flash arrangement to support features such as boot block, EEPROM Emulation, operating system block.
— 816 KB
— 264 KB
— 2128 KB
— 6256 KB
• Hardware managed Flash writes, erase and verify sequence
• Censorship protection scheme to prevent Flash content visibility
1.4.9 Static random-access memory (SRAM)
The PXD20 microcontroller has 64 KB general-purpose on-chip SRAM with the following features:
• Typical SRAM access time: 1 wait-state for reads and 32-bit writes
• 32-bit ECC with single-bit correction, double bit detection for data integrity
• Supports byte (8-bit), half word (16-bit), word (32-bit) and double-word (64-bit) writes for optimal use of memory
• User transparent ECC encoding and decoding for byte, half word, and word accesses
• Separate internal power domains applied to 56 KB and 8 KB SRAM blocks during STANDBY modes to retain
contents during low power mode.
1.4.10 On-chip graphics SRAM
The PXD20 microcontroller has 1 MB on-chip graphics SRAM with the following features:
• Two crossbar slave ports:
— One dedicated to the 2D Graphics Accelerator (GFX2D) access
— One dedicated to all other crossbar masters
• Usable as general purpose SRAM
• Supports byte (8-bit), half word (16-bit), word (32-bit) and double-word (64-bit) writes for optimal use of memory
• RAM controller with hardware RAM fill function supporting all-zeroes or all-ones SRAM initialization
• Independent data buffers (one per AHB port) for maximum system performance
— Optimized for burst transfers (read + write)
— Programmable read prefetch capabilities
PXD20 Microcontroller Data Sheet, Rev. 2
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor