PXD20 Datasheet, PDF (118/130 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Electrical characteristics
Table 66. DSPI timing¹ (continued)
Num Symbol C
Characteristic
Min
Max
Unit SpecID
7
t_SUI CC² D Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)⁸
Master (MTFE = 1, CPHA = 1)
A11.7
20
—
ns
10
—
ns
5
—
ns
35
—
ns
8
t_HI CC² D Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)⁸
Master (MTFE = 1, CPHA = 1)
A11.8
–4
—
ns
10
—
ns
26
—
ns
–4
—
ns
9 t_SUO CC² D Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA=0)
Master (MTFE = 1, CPHA=1)
A11.9
—
15
ns
—
20
ns
—
30
ns
—
15
ns
10 t_HO CC² D Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
A11.10
–15
—
ns
5.5
—
ns
0
—
ns
–15
—
ns
1 _{DSPI timing specified at VDDE_x = 3.0 V to 3.6 V, TA = –40 to 105 °C, and CL = 50 pF with SRC = 0b10.}
2 _{Parameter values guaranteed by design.}
3 _{The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate.}
4 _{The actual minimum SCK Cycle Time is limited by pad performance.}
5 _{Maximum clock possible is System clock/2.}
6 _{The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK=2 & CSSCK = 2}
7 _{The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]}
8 _{This delay value is corresponding to SMPL_PT=00b which is bit field 9 and 8 of DSPI_MCR register.}
PXD20 Microcontroller Data Sheet, Rev. 2
118
Preliminary—Subject to Change Without Notice
Freescale Semiconductor