PXD20 Datasheet, PDF (109/130 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Start of Frame
HSYNC
LD[23:0]
(Line Data)
HSYNC
t_PWV
t_HCP
t_BPV
Invalid Data
t_VSP
t_SH
1
2
3
Electrical characteristics
t_FPV
DELTA_Y Invalid Data
DE
Figure 26. Vertical sync pulse
4.18.3.2 Interface to TFT LCD panels—access level
Table 55. LCD interface timing parameters^1,2,3,4—Access Level
Num Symbol C
Characteristic
Min.
Value
Typical
Value
Max.
Value
Unit SpecID
1 t_CKP CC⁵ D PDI Clock Period
31.25
—
2 t_CHD CC⁵ D Duty cycle
40
—
3 t_DSU CC⁵ D interface data setup time
6
—
4 t_DHD CC⁵ D PDI interface data access hold time
1
—
5 t_CSU CC⁵ D PDI interface control signal setup time
3
—
6 t_CHD CC⁵ D PDI interface control signal hold time
1
—
7 — CC⁵ D TFT interface data valid after pixel clock
—
—
8 — CC⁵ D TFT interface HSYNC valid after pixel clock
—
—
9 — CC⁵ D TFT interface VSYNC valid after pixel clock
—
—
10 — CC⁵ D TFT interface DE valid after pixel clock
—
—
11 — CC⁵ D TFT interface hold time for data and control
2
—
bits
12 — CC⁵ D Relative skew between the data bits
—
—
—
ns
A3.12
60
%
A3.13
—
ns
A3.14
—
ns
A3.15
—
ns
A3.16
—
ns
A3.17
6
ns
A3.18
5
ns
A3.19
5.5
ns
A3.20
5.6
ns
A3.21
—
ns
A3.22
3.7
ns
A3.23
1 _{The characteristics in this table are based on the assumption that data is output at +ve edge and displays latch data on –ve}
edge.
2 _{Intrabit skew is less than 2 ns.}
3 _{Load CL = 50 pf for frequency up to 20 MHz.}
4 _{Load CL = 25 pf for display freq from 20 to 32 MHz.}
5 _{Parameter values guaranteed by design.}
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
109