PXD20 Datasheet, PDF (117/130 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Electrical characteristics
4.18.8 eMIOS timing
Table 64. eMIOS timing¹
Num
Symbol
C
Characteristic
Min.
value²
Max.
value
Unit SpecID
1
t_MIPW CC³ D eMIOS Input Pulse Width
2
t_MOPW CC³ D eMIOS Output Pulse Width
4
—
t_CYC
A8.1
1
—
t_CYC
A8.2
1 _{eMIOS timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = –40 to 105 °C, and}
CL = 50 pF with SRC = 0b00.
2 _{There is no limitation on the peripheral for setting the minimum pulse width, the actual width is restricted by the pad delays.}
Refer to the pad specification section for the details.
3 _{Parameter values guaranteed by design.}
4.18.9 FlexCAN timing
The CAN functions are available as TX pins at normal I/O pads and as RX pins at the always on domain.
There is no filter for the wakeup dominant pulse. Any high-to-low edge can cause wakeup if configured.
Table 65. FlexCAN timing¹
Num
Symbol
C
Characteristic
Min. value
Max.
value
Unit SpecID
1
t_CANOV CC² D CTNX Output Valid after CLKOUT Rising Edge (Output
—
Delay)
2
t_CANSU CC² D CNRX Input Valid to CLKOUT Rising Edge (Setup
—
Time)
22.48
12.46
ns A10.1
ns A10.2
1 _{FlexCAN timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = –40 to 105 °C, and CL}
= 50 pF with SRC = 0b00.
2 _{Parameter values guaranteed by design.}
4.18.10 Deserial Serial Peripheral Interface (DSPI)
Table 66. DSPI timing¹
Num
1
2
3
4
5
6
Symbol
t_SCK
t_CSC
t_ASC
t_SDC
t_A
CC²
CC²
CC²
CC²
CC²
t_DIS CC²
C
Characteristic
D SCK Cycle TIme^3,4
D PCS to SCK Delay⁶
D After SCK Delay⁷
D SCK Duty Cycle
D Slave Access Time
(PCSx active to SOUT driven)
D Slave SOUT Disable Time
(PCSx inactive to SOUT High-Z or invalid)
Min
60⁵
—
20
t_SCK/2 – 2ns
—
Max
—
—
—
t_SCK/2 + 2ns
25
Unit
ns
ns
ns
ns
ns
SpecID
A11.1
A11.2
A11.3
A11.4
A11.5
—
25
ns
A11.6
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
117