PXD20 Datasheet, PDF (13/130 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

1.4.11 Memory Protection Unit (MPU)
The MPU features the following:
• Sixteen region descriptors for per master protection
• Start and end address defined with 32-byte granularity
• Overlapping regions supported
• Protection attributes can optionally include process ID
• Protection offered for 4 concurrent read ports
• Read and write attributes for all masters
• Execute and supervisor/user mode attributes for processor masters
Overview
1.4.12 2D graphics accelerator (GFX2D)
• Native vector graphics rendering
— Compatible with OpenVG1.1
— Complete hardware OpenVG 1.1 rendering pipeline
— Both geometry and pixel processing
— Adaptive processing of Bezier curves and strokes
• 16-sample edge anti-aliasing
— High image quality, font scalability, etc.
— 4 Rotated Grid Supersampling (RGSS) AA for Flash
• 3D perspective texturing, reflections, and shadowing
• Shading (linear or radial gradient)
• Separate 2D engine for BitBlt, fill and ROP operations
• Significant performance improvement when compared to software or 3D GPU-based OpenVG implementations
1.4.13 Display Control Unit (DCU3)
The DCU3 is a display controller designed to drive TFT LCD displays up to WVGA resolution using direct blit graphics and
video.
The DCU3 generates all the necessary signals required to drive the TFT LCD displays: up to 24-bit RGB data bus, Pixel Clock,
Data Enable, Horizontal-Sync and Vertical-Sync.
The flexible architecture of the DCU3 enables the display of OpenVG-rendered frame buffer content and direct blit rendered
graphics simultaneously.
An optional Timing Controller (TCON) and RSDS interface is available to directly drive the row and column drivers of a
display panel.
Internal memory resource of the device allows to easily handle complex graphics contents (pictures, icons, languages, fonts).
The DCU3 supports 4-plane blending and 16 graphics layers. Control Descriptors (CDs) associated with each of the 16 layers
enable effective merging of different resolutions into one plane to optimize use of internal memory buffers. A layer may be
constructed from graphic content of various resolutions including indexed colors of 1, 2, 4 and 8 bpp, direct colors of 16, 24
and 32 bpp, and a YUV 4:2:2 color space. The ability of the DCU3 to handle input data in resolutions as low as 1bpp, 2bpp and
4bpp enables a highly efficient use of internal memory resources of the PXD20. A special tiled mode can be enabled on any of
the 16 layers to repeat a pattern optimizing graphic memory usage.
A hardware cursor can be managed independently of the layers at blending level increasing the efficient use of the internal
DCU3 resources.
PXD20 Microcontroller Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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