PXD20 Datasheet, PDF (34/130 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Pinout and signal descriptions
Table 6. DRAM interface pin summary (continued)
Port pin¹
Function
I/O
direction
Pad
type
PCR
RESET
config²
DDR_CLKB DRAM Clock bar
Output
DDR
NA
Output,
None
DDR_CK
DRAM Clock Enable
Output
DDR
PCR[222] Output,
Pull Down
DDR_CS
DRAM Chip Select
Output
DDR
PCR[223] Output,
None
MVREF
DDR Reference Voltage
Input
—
NA
—
MVTT
DRAM Termination Voltage
Input
—
NA
—
1 _{These port pins are disabled and unpowered on packages where the DRAM interface is not bonded out.}
2 _{Reset configuration is given as I/O direction and pull direction (for example, “Input, pullup”).}
Pin number
416 TEPBGA
D7
D8
D9
J4
F2,J2,M2,R2
2.4.7 VIU muxing
The DCU3, DCULite and VIU2 modules share the same pins for input video. It is, however, possibile to feed independent video
streams to VIU2 and DCU3 (operating in narrow mode). Figure 5 explains the pin sharing arrangement.
DE
PDI_PCLK
VSYNC
HSYNC
DATA[17:0]
VIU_PCLK
Direct feed of PDI interface
to DCU3 or DCULite
VIU[9:0]
VIU2
DCU3
DCULite
PDI
PDI
RGB565
RGB888
8-bit mono
YUV422
XBAR
Figure 5. VIU2, DCU3, and DCULite pin sharing
VIU input data selection is done based on select bit (bit 0) of Miscellaneous control register (0xC3FE0340).
• VIU pix data: VIU[9:0]
• Select bit 1’b0: PDI[7:0],HSYNC,VSYNC
• Select bit 1’b1: PDI[17:8]
PXD20 Microcontroller Data Sheet, Rev. 2
34
Preliminary—Subject to Change Without Notice
Freescale Semiconductor