908E621_07 Datasheet, PDF (59/62 Pages) Freescale Semiconductor, Inc – Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror

ADDITIONAL INFORMATION
THERMAL ADDENDUM (REV 1.0)
PTC4 /OSC1
1
PTC3 /OSC2
2
PTC2 / MCLK
3
PTB5 /AD5
4
PTB4 /AD4
5
PTB3 /AD3
6
IRQ
7
RST
8
(PTD0/TACH0/BEMF -> PWM)
9
PTD1/TACH1
10
RST_A
11
IRQ_A
12
LIN
13
A0CST
14
A0
15
GND1
16
HB4
17
VSUP1
18
GND2
19
HB3
20
VSUP2
21
NC
22
NC
23
TESTMODE
24
GND3
25
HB2
26
VSUP3
27
Exposed
Pad
54
PTA0 / KBD0
53
PTA1 / KBD1
52
PTA2 / KBD2
51
FLSVPP
50
PTA3 / KBD3
49
PTA4 / KBD4
48
VDDA/VREFH
47
EVDD
46
EVSS
45
VSSA/VREFL
44
(PTE1/RXD <- RXD)
43
VSS
42
VDD
41
HVDD
40
L0
39
H0
38
HS3
37
VSUP8
36
HS2
35
VSUP7
34
HS1b
33
HS1a
32
VSUP6
31
VSUP5
30
GND4
29
HB1
28
VSUP4
A
908E621 Terminal Connections
54-Terminal SOICW-EP
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
Figure 35. Thermal Test Board
Device on Thermal Test Board
Material:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
Outline:
80 mm x 100 mm board area,
including edge connector for
thermal testing
Area A:
Cu heat-spreading areas on board
surface
Ambient Conditions: Natural convection, still air
Table 25. Thermal Resistance Performance
Thermal
Resistance
Area A
(mm²)
1 = Power Chip, 2 = Logic Chip (°C/W)
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
R_θJAmn
0
53
48
53
300
39
34
38
600
35
30
34
R_θJSmn
0
21
16
20
300
15
11
15
600
14
9.0
13
R_θJA is the thermal resistance between die junction and
ambient air.
R_θJSmn is the thermal resistance between die junction and
the reference location on the board surface near a center
lead of the package. This device is a dual die package. Index
m indicates the die that is heated. Index n refers to the
number of the die where the junction temperature is sensed.
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E621
59