908E621_07 Datasheet, PDF (43/62 Pages) Freescale Semiconductor, Inc – Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SRS0-1 — LIN Slew rate Select Bits
These read/write bits enable the user to select the
appropriate LIN slew rate for different Baudrate
configurations.
Reset clears the SRS1:0 bits.
Table 11. LIN Slew Rate Selection Bits
SRS1
SRS0
Slew rate
0
0
Initial Slew Rate (20kBaud)
0
1
High Speed II (8x)
1
0
Slow Slew Rate (10kBaud)
1
1
High Speed I (4x)
The high speed slew rates are used, for example, for
programming via the LIN and are not intended for use in the
application.
System Status Register (SYSSTAT)
Register Name and Address: SYSSTAT - $0C
Bit7 6
5
4
3
2
1 Bit0
Read LINC HTIF VF H0F HVD HSF HBF 0
L
DF
Write
Reset 0
0
0
0
0
0
0
0
LINCL — LIN Current Limitation Bit
This read only bit is set if the LIN transmitter operates in
current limitation region. Due to excessive power dissipation
in the transmitter, the driver will be automatically turned off
after a certain time.
1 = transmitter operating in current limitation region
0 = transmitter not operating in current limitation region
HTIF— Overtemperature Status Bit
This read only bit is a copy of the HTIF bit in the Interrupt
Flag register
1 = overtemperature condition
0 = no overtemperature condition
VF — Voltage Failure Bit
This read only bit indicates that the supply voltage was out
of the allowed range. The bit is set if either the LVIF or the
HVIF in the Interrupt Flag register is set.
1 = low/high voltage condition detected
0 = no voltage failure condition detected
HVIF
VF
LVIF
Figure 25. VF flag generation
Analog Integrated Circuit Device Data
Freescale Semiconductor
H0F — H0 Failure Bit
This read only bit is a copy of the H0OCF bit in the H0/L0
Status and Control Register (HLSCTL)
1 = overcurrent detected on H0
0 = no overcurrent on H0
HVDDF— HVDD Failure Bit
This read only bit is a copy of the HVDDOCF bit in the
High-Side Status register
1 = HVDD terminal fail
0 = HVDD normal operating
HSF— HS1:3 Failure Bit
This read only bit is set if a fail condition on one of the high-
side outputs is present
1 = HS1:3 terminal fail
0 = HS1:3 normal operating
HS1OCF
HS2OCF
HS3OCF
HSF
Figure 26. HSF flag generation
HBF— HB1:4 Failure Bit
This read only bit is set if a fail condition on one of the half
bridge outputs is present.
1 = HB1:4 terminal overcurrent fail
0 = HB1:4 normal operating
HB1OCF
HB2OCF
HB3OCF
HB4OCF
HBF
Figure 27. HBF flag generation
WINDOW WATCHDOG
The window watchdog is to supervise the device and to
recover from e.g. code runaways or similar conditions.
The use of a window watchdog adds additional safety as
the watchdog clear has not only to occur but to be done at a
certain time frame / window.
Normal mode
The window watchdog function is just available in Normal
mode and is ceased in Stop and Sleep mode. On setting the
WDRE bit, the watchdog functionality is activated. Once this
908E621
43