908E621_07 Datasheet, PDF (28/62 Pages) Freescale Semiconductor, Inc – Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
INTERRUPT MASK REGISTER (IMR)
Register Name and Address: IMR - $09
Bit7 6
5
4
3
2
1 Bit0
Read
Write
L0IE
H0IE LINIE HTRD HTIE
LVIE
HVIE PSFIE
Reset 0
0
0
0
0
0
0
0
L0IE - L0 Input Interrupt Enable Bit
This read/write bit enables CPU interrupts by the L0 flag,
L0IF. Reset clears the L0IE bit.
1 = interrupt requests from L0IF flag enabled
0 = interrupt requests from L0IF flag disabled
H0IE - H0 Input Interrupt Enable Bit
This read/write bit enables CPU interrupts by the Hallport
flag, H0IF. Reset clears the H0IE bit.
1 = interrupt requests from H0IF flag enabled
0 = interrupt requests from H0IF flag disabled
LINIE - LIN line Interrupt Enable Bit
This read/write bit enables CPU interrupts by the LIN flag,
LINIF. Reset clears the LINIE bit.
1 = interrupt requests from LINIF flag enabled
0 = interrupt requests from LINIF flag disabled
HTRD - High Temperature Reset Disable Bit
This read/write bit disables the high temperature reset
function. Reset clears the HTRD bit.
1 = high temperature reset is disabled
0 = high temperature reset is enabled
Note: Disabling of the high temperature reset can lead
to a destruction of the part in cases of high temperature.
This bit was foreseen for test purposes only!
HTIE - High Temperature Interrupt Enable Bit
This read/write bit enables CPU interrupts by the high
temperature flag, HTIF. Reset clears the HTIE bit.
1 = interrupt requests from HTIF flag enabled
0 = interrupt requests from HTIF flag disabled
LVIE - Low Voltage Interrupt Enable Bit
This read/write bit enables CPU interrupts by the low
voltage flag, LVIF.Reset clears the LVIE bit.
1 = interrupt requests from LVIF flag enabled
0 = interrupt requests from LVIF flag disabled
HVIE - High Voltage Interrupt Enable Bit
This read/write bit enables CPU interrupts by the high
voltage flag, HVIF.Reset clears the HVIE bit.
1 = interrupt requests from HVIF flag enabled
0 = interrupt requests from HVIF flag disabled
PSFIE - Power Stage Fail Interrupt Enable Bit
This read/write bit enables CPU interrupts by power stage
fail flag, PSFIF. Reset clears the PSFIE bit.
1 = interrupt requests from PSFIF flag enabled
0 = interrupt requests from PSFIF flag disabled
908E621
28
Analog Integrated Circuit Device Data
Freescale Semiconductor