908E621_07 Datasheet, PDF (38/62 Pages) Freescale Semiconductor, Inc – Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Half-Bridge Control
Each output MOSFET can be controlled individually. The
general enable of the circuitry is done by setting PSON in the
System Control Register (SYSCTL). The HBx_L and HBx_H
bits form one half bridge. It is not possible to switch on both
MOSFETs in one half-bridge at the same time. If both bits are
set, the high-side MOSFET is in PWM mode.
To avoid both MOSFETs (high-side and low-side) of one
half-bridge being on at the same time, a break-before-make
circuit exists. Switching the high-side MOSFET on is inhibited
as long as the potential between gate and V_SS is not below a
certain threshold. Switching the low-side MOSFET on is
blocked as long as the potential between gate and source of
the high-side MOSFET did not fall below a certain threshold.
HALF-BRIDGE OUTPUT REGISTER (HBOUT)
Register Name and Address: HBOUT - $01
Bit7 6
5
4
3
2
1 Bit0
Read
Write
HB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L
Reset 0
0
0
0
0
0
0
0
HBx_H, HBx_L — Half Bridge Output Switches
These read/write bits select the output of each half-bridge
output according to the following table.
Reset clears all HBx_H, HBx_L bits.
Table 9. Half-Bridge Configuration
HBx_H HBx_L
Mode
0
0
Low-side and high-side MOSFET off
0
1
High-side MOSFET off,
low-side MOSFET on
1
0
High-side MOSFET on,
low-side MOSFET off
1
1
High-side MOSFET in PWM mode
Half-Bridge PWM mode
The PWM mode is selected by setting both HBxL and
HBxH of one Half-bridge to “1”. In this mode the high-side
MOSFET is controlled by the incoming PWM signal on the
PWM terminal (see Figure 2, page 2).
If the incoming signal is high, the high-side MOSFET is
switched on.
If the incoming signal is low, the high-side MOSFET is
switched off.
With the current recirculation mode control bit CRM in the
Half-Bridge Status and Control Register (HBSCTL) the
recirculation behavior in PWM mode can be controlled. If
CRM is set the corresponding low-side MOSFET is switched
on if the PWM controlled high-side MOSFET is off.
Half-Bridge Current Recopy
Each low-side MOSFET has an additional sense output to
allow a current recopy feature. These sense sources are
internally amplified and switched to the Analog Multiplexer.
The factor for the Current Sense amplification can be
selected via bit CSA in the A0MUCTL register (see page 32)
CSA = “1”: low resolution selected
CSA = “0”: high resolution selected
Half-Bridge Overtemperature Protection
The outputs are protected against overtemperature
conditions. Each power output comprises two different
temperature thresholds.
The first threshold is the high temperature interrupt (HTI).
If the temperature reaches this threshold the HTIF bit in the
Interrupt Flag Register (IFR) is set and an interrupt will be
initiated if HTIE bit in the Interrupt Mask register is set. In
addition this interrupt can be used to automatically turn off the
power stages. This shutdown can be enabled/disabled by
Bits HTIS0-1 in the System Control Register (SYSCTL).
The high temperature interrupts flag (HTIF) is cleared (and
the outputs reenabled) by writing a “1” to the HTIF flag in the
Interrupt Flag Register (IFR) or by a reset. Clearing this flag
has no effect as long as a high temperature condition is
present.
If the HTI shutdown is disabled, a second threshold high
temperature reset (HTR) will be used to turn off all power
stages (HB (all Fet’s), HS, HVDD, H0) in order to protect the
device.
Half-Bridge Overcurrent Protection
The Half-Bridges are protected against short to GND,
VSUP and load shorts. The overcurrent protection is
implemented on each HB. If a overcurrent condition on the
high-side MOSFET occurs the high-side MOSFET is
automatically switched off. An overcurrent condition on the
low-side MOSFET will automatically turn off the low-side
MOSFET. In both cases the corresponding HBxOCF flag in
the Half-Bridge Status and Control Register (HBSCTL) is set.
The overcurrent status flag is cleared (and the
corresponding Half-Bridge MOSFETs reenabled) by writing a
“1” to the HBxOCF in the Half-Bridge Status and Control
Register (HBSCTL) or by a reset.
908E621
38
Analog Integrated Circuit Device Data
Freescale Semiconductor