908E621_07 Datasheet, PDF (42/62 Pages) Freescale Semiconductor, Inc – Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HSxPWM — High-Side PWM on/off Bits
These read/write bits enable the PWM control of the High-
Side Fet’s.
Reset clears the HSxPWM bits.
1 = High-Side x is controlled by PWM input signal
0 = High-Side x is not controlled by PWM input signal
High-Side Status Register (HSSTAT)
Register Name and Address: HSSTAT - $04
Bit7
6
5
4
3
2
1
Bit0
Read
0
0
0
0
HVDD
HS3O HS2O HS1O
OCF
Write
CF CF CF
Reset 0
0
0
0
0
0
0
0
HSxOCF — High-Side Overcurrent Flag Bit
This read/write flag is set by an overcurrent condition at
the high-side drivers x.
Clear HSxOCF and enable the HS Driver by writing a logic [1]
to HSxOCF. Writing a logic [0] to HSxOCF has no effect.
Reset clears the HSxOCF bit.
1 = overcurrent condition on high-side drivers has
occurred
0 = no overcurrent condition on high-side drivers has
occurred
HVDDOCF — HVDD Output Overcurrent Flag Bit
This read/write flag is set by an overcurrent condition at
HVDD terminal. Clear HVDDOCF and enable the output by
writing a logic [1] to the HVDDOCF Flag. Writing a logic [0] to
HVDDOCF has no effect.
Reset clears the HVDDOCF bit.
1 = overcurrent condition on VDD output has occurred
0 = no overcurrent condition on VDD output has
occurred
System Control Register (SYSCTL)
Register Name and Address: SYSCTL - $00
Bit7 6
5
4
3
2
1 Bit0
Read
0
0
PSON
HTIS1 HTIS0 VIS SRS1 SRS0
Write
STOP SLEEP
Reset 0
0
0
0
0
0
0
0
PSON — Power Stages On Bit
This read/write bit enables the power stages (half bridges,
high-sides, LIN transmitter, A0 Current Sources and HVDD
output).
Reset clears the PSON bit.
1 = power stages enabled
0 = power stages disabled
STOP — Change to STOP Mode Bit
This write bit instructs the chip to enter Stop mode (See
Operational Modes on page 24).
Reset or CPU interrupt requests clear the STOP bit.
1 = go to Stop mode
0 = not in stop mode
In order to safely Stop mode all other bits (Bit7-Bit2) have
to be “0”. Otherwise the STOP command will not be
executed.
SLEEP — Change to SLEEP Mode Bit
This write bit instructs the chip to enter Sleep mode (See
Operational Modes on page 24).
Reset or CPU interrupt requests clear the SLEEP bit.
1 = go to Sleep mode
0 = not in sleep mode
In order to safely enter Sleep mode all other bits (Bit7-Bit2)
have to be “0”. Otherwise the SLEEP command will not be
executed.
HTIS0-1 — High Temperature Interrupt Shutdown Bits
This read/write bits selects the power stage behavior at
High Temperature Interrupt (HTI).
Reset clears the HTIS0-1 bits.
The HTIS0 bit selects the behavior of the high-side HS1:3
and the high-side FET of the half-bridges HB1:4.
1 = automatic HTI shutdown of the high-side drivers
disabled
0 = automatic HTI shutdown of the high-side drivers
enabled
The HTIS1 bit selects the behavior of the low-side drivers
of the half-bridges HB1:4.
1 = automatic HTI shutdown of the low-side drivers
disabled
0 = automatic HTI shutdown of the low-side drivers
enabled
The user has to take care to protect the device against
thermal destruction!
VIS — Over-/Undervoltage Interrupt Shutdown
This read/write bit selects the power stage behavior at LVI/
HVI.
Reset clears the VIS bit.
1 = automatic LVI/HVI shutdown disabled
0 = automatic LVI/HVI shutdown enabled
908E621
42
Analog Integrated Circuit Device Data
Freescale Semiconductor