908E621_07 Datasheet, PDF (50/62 Pages) Freescale Semiconductor, Inc – Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Analog Die System Trim Values
For improved application performance and to ensure the
outlined datasheet values the analog die needs to be
trimmed. For this purpose 3 trim values are stored in the
Flash memory at address $FDC4 - $FDC6. These values
have to be copied into the analog die SPI registers:
• copy $FDC4 into SYSTRIM1 register $0F
• copy $FDC5 into SYSTRIM2 register $10
• copy $FDC6 into SYSTRIM3 register $11
Note: This values have to be copied to the respective SPI
register after a reset to ensure proper trimming of the device.
System Test Register (SYSTEST)
Register Name and Address: SYSTEST - $0E
Bit7 6
5
4
3
2
1 Bit0
Read
Write
reserved reserved reserved reserved reserved reserved reserved reserved
Reset 0
0
0
0
0
0
0
0
Note: do not write to the reserved bits
The System Test Register is reserved for production
testing and is not allowed to be written to.
System Trim Register 1 (SYSTRIM1)
HVDDT1
1
HVDDT0
1
typical Delay
78us
ITRIM3:0 - IRef Trim Bits
These write only bits are for trimming of the internal
current references IRef (also A0, A0CST). The provided
trim values have to be copied into these bits after every
reset. Reset clears the ITRIM3:0 bits.
itrim3
0
0
0
0
0
0
0
0
1
Table 16. IRef Trim Bits
itrim2 itrim2 itrim0 Adjustment
0
0
0
0
0
0
1
2%
0
1
0
4%
0
1
1
8%
1
0
0
12%
1
0
1
-2%
1
1
0
-4%
1
1
1
-8%
0
0
0
-12%
Register Name and Address: IBIAS - $0F
Bit7 6
5
4
3
2
1 Bit0
Read
Write
HVDDT1 HVDDT0
0
0
ITRIM3 ITRIM2 ITRIM1 ITRIM0
reserved reserved
Reset 0
0
0
0
0
0
0
0
Note: do not change (set) the reserved bits
HVDDT1:0 - HVDD Overcurrent Shutdown Delay Bits
These read/write bits allow to change the filter time (for
capacitive load) for the HVDD over current detection.
Reset clears the HVDDT1:0 bits an sets the delay to the
maximum value.
Table 15. HVDD Overcurrent Shutdown Selection Bits
HVDDT1
HVDDT0
typical Delay
0
0
950us
0
1
536us
1
0
234us
908E621
50
System Trim Register 2 (SYSTRIM2)
Register Name and Address: IFBHBTRIM - $10
Bit7 6
5
4
3
2
1 Bit0
Read ⁰
0
0
0
0
0
0
0
Write ^{CRHBHC1 CRHBHC0 CRHB5 CRHB4 CRHB3 CRHB2 CRHB1 CRHB0}
Reset 0
0
0
0
0
0
0
0
CRHBHC1:0 - Current Recopy HB1:2 Trim Bits
These write only bits are for trimming of the current
recopy of the half-bridge HB1 and HB2 (CSA=0). The
provided trim values have to be copied into these bits
after every reset. Reset clears the CRHBHC1:0 bits.
Table 17. Current Recopy Trim for HB1:2 (CSA=0)
CRHBHC1 CRHBHC0
Adjustment
0
0
0
0
1
-10%
Analog Integrated Circuit Device Data
Freescale Semiconductor