908E621_07 Datasheet, PDF (23/62 Pages) Freescale Semiconductor, Inc – Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror

FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
INTERRUPT TERMINAL (IRQ_A)
IRQ_A is the interrupt output terminal of the analog die
indicating errors or wake-up events. It is an open drain with
pullup resistor and must be connected to the IRQ terminal of
the MCU.
ADC SUPPLY/REFERENCE TERMINALS (VDDA/
VREFH AND VSSA/VREFL)
VDDA and VSSA are the power supply terminals for the
analog-to-digital converter (ADC).
VREFH and VREFL are the reference voltage terminals for
the ADC.
The supply and reference signals are internally connected.
It is recommended that a high quality ceramic decoupling
capacitor be placed between these terminals.
For details refer to the 68HC908EY16 datasheet.
MCU POWER SUPPLY TERMINALS (EVDD AND
EVSS)
EVDD and EVSS are the power supply and ground
terminals. The MCU operates from a single power supply.
Fast signal transitions on MCU terminals place high, short-
duration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU.
For details refer to the 68HC908EY16 datasheet.
VDDA/VREFH
EVDD
µC
VDD
0,1µF 4,7µF
Analog
Die
TEST MODE TERMINAL (TESTMODE)
This terminal is for test purpose only. In the application this
terminal has to be forced to GND.
For Programming/Test this terminal has to be forced to
VDD to bring the analog die into Test mode. In Test mode the
Reset Time-out (80ms) is disabled and the LIN receiver is
disabled
NOTE: After detecting a RESET (internal or external) the
PSON bit needs to be set within 80ms. If not the device will
automatically enter sleep mode.
MCU TEST TERMINAL (FLSVPP)
This terminal is for test purposes only. This terminal should
be either left open (not connected) or can be connected to
GND.
NO CONNECT TERMINALS (NC)
The NC terminals are not connected internally.
Note: Each of the NC terminals can be left open or
connected to ground (recommended).
EXPOSED PAD TERMINAL
The exposed pad terminal on the bottom side of the
package conducts heat from the chip to the PCB board. For
thermal performance the pad must be soldered to the PCB
board. It is recommended that the pad be connected to the
ground potential.
EVSS
VSSA/VREFL
VSS
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E621
23