908E621_07 Datasheet, PDF (15/62 Pages) Freescale Semiconductor, Inc – Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror

DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ V_SUP ≤ 16 V, -40°C ≤ T_J ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T_A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER
Driver Characteristics for Normal Slew Rate ^{(25), (26)}
Dominant Propagation Delay TXD to LIN
t _DOM-MIN
—
—
50
µs
Dominant Propagation Delay TXD to LIN
t _DOM-MAX
—
—
50
µs
Recessive Propagation Delay TXD to LIN
t _REC-MIN
—
—
50
µs
Recessive Propagation Delay TXD to LIN
t _REC-MAX
—
—
50
µs
Duty Cycle 1: D1 = t_{Bus_rec(min)} / (2 x t_BIT), t_BIT = 50 µs, V_SUP = 7.0V..18V
D1
0.396
–
–
Duty Cycle 2: D2 = t_{Bus_rec(max)} / (2 x t_BIT), t_BIT = 50 µs, V_SUP = 7.6V..18V
D2
Driver Characteristics for Slow Slew Rate ^{(25), (27)}
–
–
0.581
Dominant Propagation Delay TXD to LIN
t _DOM-MIN
—
—
100
µs
Dominant Propagation Delay TXD to LIN
t _DOM-MAX
—
—
100
µs
Recessive Propagation Delay TXD to LIN
t _REC-MIN
—
—
100
µs
Recessive Propagation Delay TXD to LIN
t _REC-MAX
—
—
100
µs
Duty Cycle 3: D3 = t_{Bus_rec(min)} / (2 x t_BIT), t_BIT = 96 µs, V_SUP = 7.0V..18V
D3
0.417
–
–
Duty Cycle4: D4 = t_{Bus_rec(max)} / (2 x t_BIT), t_BIT = 96 µs, V_SUP = 7.6V..18V
D4
–
–
0.590
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
Receiver Characteristics and Wake-Up Timings
SR_FAST
—
20
—
V / µs
Receiver Dominant Propagation Delay ⁽²⁸⁾
Receiver Recessive Propagation Delay ⁽²⁸⁾
Receiver Propagation Delay Symmetry
Bus Wake-Up Deglitcher
Bus Wake-Up Event Reported ⁽²⁹⁾
t _RL
—
3.5
6.0
µs
t _RH
—
3.5
6.0
µs
t _R-SYM
- 2.0
—
2.0
µs
t _PROPWL
30
50
150
µs
t _WAKE
—
20
—
µs
Notes
25. V_SUP from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 kΩ, 6.8 nF/660 Ω, 10 nF/500 Ω. Measurement thresholds: 50% of TXD signal
to LIN signal threshold defined at each parameter.
26. See Figure 6, page 18.
27. See Figure 7, page 19.
28. Measured between LIN signal threshold V_IL or V_IH and 50% of RXD signal.
29. t_WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 9 and Figure 8, page 19. In Sleep mode the V_DD
rise time is strongly dependent upon the decoupling capacitor at VDD terminal.
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E621
15