908E621_07 Datasheet, PDF(30/62 Page) Freescale Semiconductor, Inc – Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror

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908E621_07 Datasheet, PDF (30/62 Pages) Freescale Semiconductor, Inc – Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror

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FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

In addition the register includes two flags which will

indicate the source of a wake-up from Sleep mode: Either LIN

bus activity or an event on the L0 wake-up input terminal.

Bit7 6

1 Bit0

Read

POR PINR WDR HTR LVR

Write

LINWF LOWF

POR 1

PORâ Power On Reset bit

This read/write bit is set after power on. Bit is cleared by

writing a logic â1â to this location.

1 = Reset due to power on

0 = no power on reset

PINRâ Reset forced from external Reset terminal bit

This read/write bit is set after an reset was forced on the

external reset RST_A terminal. Bit is cleared by writing an

logic â1â to this location.

1 = reset source is external reset terminal

0 = no external reset

WDRâ Watch Dog Reset bit

This read/write flag is set due to watchdog time-out or

wrong watchdog timer reset. Clear WDR by writing a logic â1â

to WDR.

1 = reset source is watchdog

0 = no watchdog reset

HTRâ High Temperature Reset bit

This read/write bit is set if the chip temperature exceeds a

certain value. Bit is cleared by writing a logic â1â to this

location.

1 = reset due to high temperature condition

0 = no high temperature reset

LVRâ Low Voltage Reset bit

This read/write bit is set if the external VDD voltage

coming from the main voltage regulator falls below a certain

value. Bit is cleared by writing a logic â1â to this location.

1 = reset due to low voltage condition

0 = no low voltage reset

LINWFâ LIN Wake-Up Flag

This read/write bit is set if a bus activity was the case of an

wake-up. Bit is cleared by writing a logic â1â to this location.

1 = Wake-up due to bus activity

0 = no wake-up due to bus activity

L0WFâ L0 Wake-Up Flag

This read/write bit is set if a event on the L0 terminal

caused an wake-up. Bit is cleared by writing a logic â1â to this

location.

1 = Wake-Up due to L0 terminal

0 = no Wake-Up due to L0 terminal

ANALOG DIE INPUTS/OUTPUTS

LIN PHYSICAL LAYER

The LIN bus terminal provides a physical layer for single-

wire communication in automotive applications. The LIN

physical layer is designed to meet the LIN physical layer

specification.

The LIN driver is a low-side MOSFET with internal current

limitation and thermal shutdown. An internal pullup resistor

with a serial diode structure is integrated, so no external

pullup components are required for the application in a slave

node. The fall time from dominant to recessive and the rise

time from recessive to dominant is controlled. The symmetry

between both slew rate controls is guaranteed.

The slew rate can be selected for optimized operation at

10 and 20kBit/s as well as high baud rates for test and

programming. The slew rate can be adapted with 2 bits

SRS[1:0] in the System Control Register. The initial slew rate

is optimized for 20kBit/s.

The LIN terminal offers high susceptibility immunity level

from external disturbance, guaranteeing communication

during external disturbance.

The LIN transmitter circuitry is enabled by setting the

PSON bit in the System Control Register (SYSCTL).

If the transmitter works in the current limitation region, the

LINCL bit in the System Status Register (SYSSTAT) is set

and the LIN transceiver is disabled after a certain time.

908E621

Analog Integrated Circuit Device Data

Freescale Semiconductor

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