908E621_07 Datasheet, PDF (27/62 Pages) Freescale Semiconductor, Inc – Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
input). The interrupt function is available if the input is
selected as General Purpose or as 2pin Hallsensor input. The
interrupt is maskable with the H0IE bit in the Interrupt Mask
Register.
During Stop and Sleep mode the H0I circuitry is disabled.
L0 input Interrupt
The L0 interrupt flag L0IF is set in run mode by a state
change of the L0F flag (rising or falling edge). The interrupt is
maskable with the L0IE bit in the interrupt mask register.
INTERRUPT FLAG REGISTER (IFR)
Register Name and Address: IFR - $0A
Bit7 6
5
4
3
2
1 Bit0
Read
PSFIF
L0IF H0IF LINIF 0 HTIF LVIF HVIF
Write
Reset 0
0
0
0
0
0
0
0
L0IF - L0 Input Flag Bit
This read/write flag is set on a falling or rising edge at the
L0 input. Clear L0IF by writing a logic [1] to L0IF.
Reset clears the L0IF bit. Writing a logic [0] to L0IF has no
effect.
1 = rising or falling edge on L0 input detected
0 = no state change on L0 input detected
H0IF - H0 Input Flag Bit
This read/write flag is set on a falling or rising edge at the
H0 input. Clear H0IF by writing a logic [1] to H0IF.
Reset clears the H0IF bit. Writing a logic [0] to H0IF has no
effect.
1 = state change on the hallflags detected
0 = no state change on the hallflags detected
LINIF - LIN Flag Bit
This read/write flag is set if a rising edge is detected and
the bus was dominant longer than TpropWL. Clear LINIF by
writing a logic [1] to LINIF. Reset clears the LINIF bit. Writing
a logic [0] to LINIF has no effect.
1 = LIN bus interrupt has occurred
0 = not LIN bus interrupt occurred since last clear
HTIF - High Temperature Flag Bit
This read/write flag is set on high temperature condition.
Clear HTIF by writing a logic [1] to HTIF. If high temperature
condition is still present while writing a logical one to HTIF,
the writing has no effect. Therefore, a high temperature
interrupt cannot be lost due to inadvertent clearing of HTIF.
Reset clears the HTIF bit. Writing a logic [0] to HTIF has no
effect.
1 = high temperature condition has occurred
0 = high temperature condition has not occurred
LVIF - Low Voltage Flag Bit
This read/write flag is set on low voltage condition. Clear
LVIF by writing a logic [1] to LVIF. If low voltage condition is
still present while writing a logical one to LVIF, the writing has
no effect. Therefore, a low voltage interrupt cannot be lost
due to inadvertent clearing of LVIF.
Reset clears the LVIF bit. Writing a logic [0] to LVIF has no
effect.
1 = low voltage condition has occurred
0 = low voltage condition has not occurred
HVIF - High Voltage Flag Bit
This read/write flag is set on high voltage condition. Clear
HVIF by writing a logic [1] to HVIF. If high voltage condition is
still present while writing a logical one to HVIF, the writing has
no effect. Therefore, a high voltage interrupt cannot be lost
due to inadvertent clearing of HVIF.
Reset clears the HVIF bit. Writing a logic [0] to HVIF has no
effect.
1 = high voltage condition has occurred
0 = high voltage condition has not occurred
PSFIF - Power Stage Fail Bit
This read-only flag is set on a fail condition on one of the
power outputs (HBx, HSx, HVDD, H0). Reset clears the
PSFIF bit. Clear this flag, by writing a logic [1] to the
appropriate fail flag.
1 = power stage fail condition has occurred
0 = power stage fail condition has not occurred
H0OCF
HVDDOCF
HB1OC
HB2OC
HB3OC
HB4OC
HS1OC
HS2OC
HS3OC
H0OCF
HVDDOCF
HBFF
HSFF
PSFIF
Figure 14. Principal Implementation of the PSFIF
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E621
27