ES29LV160F Datasheet, PDF (36/71 Pages) Excel Semiconductor Inc. – 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

ES29LV160F
Excel Semiconductor Inc.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the
Embedded Program algorithm is complete.
Table 11.1 on page 38 shows the outputs for Toggle Bit I on DQ6. Figure 11.2 on page 37 shows
the toggle bit algorithm in flowchart form, and Reading Toggle Bits DQ6/DQ2 on page 36 explains
the algorithm. Figure 17.9 on page 51 shows the toggle bit timing diagrams. Figure 17.10 on page
52 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on
DQ2: Toggle Bit II on page 36.
11.4 DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for
erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot
distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison,
indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status bits are required for sector and mode
information. Refer to Table 11.1 on page 38 to compare outputs for DQ2 and DQ6.
Figure 11.2 on page 37 shows the toggle bit algorithm in flowchart form, and the section Reading
Toggle Bits DQ6/DQ2 on page 36 explains the algorithm. See also the DQ6: Toggle Bit I on page
35 subsection. Figure 17.9 on page 51 shows the toggle bit timing diagram. Figure 17.10 on page
52 shows the differences between DQ2 and DQ6 in graphical form.
11.5 Reading Toggle Bits DQ6/DQ2
Refer to Figure 11.2 on page 37 for the following discussion. Whenever the system initially begins
reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the
first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling,
the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the
system should then determine again whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has
successfully completed the program or erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
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