ES29LV160F Datasheet, PDF (24/71 Pages) Excel Semiconductor Inc. – 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

ES29LV160F
Excel Semiconductor Inc.
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0000h
Page Mode Type
00 = Not Supported, 01 =4 Word Page, 02 = Word Page
4Dh
9Ah
00B5h
ACC(Acceleration) Supply Minimum
00 = Not Supported, D7-D4: Volt, D3-D0:100mV
4Eh
9Ch
00C5h
ACC(Acceleration) Supply Maximum
00 = Not Supported, D7-D4: Volt, D3-D0:100mV
4Fh
9Eh
000xh
Top/Bottom Boot Sector Flag
3 = Top, 2 = Bottom
8.1 Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes (refer to Table 10.1 on page 32 for command definitions). In
addition, the following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals during V_CC
power-up and power-down transitions, or from system noise.
8.1.1 Low V_CC Write Inhibit
When V_CC is less than VLKO, the device does not accept any write cycles. This protects data
during V_CC power-up and power-down. The command register and all internal program/erase
circuits are disabled, and the device resets. Subsequent writes are ignored until V_CC is greater than
VLKO. The system must provide the proper signals to the control pins to prevent unintentional
writes when V_CC is greater than VLKO.
8.1.2 Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.1.3 Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a
write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Rev.0A (Dec 12, 2007) 24