ES29LV160F Datasheet, PDF (29/71 Pages) Excel Semiconductor Inc. – 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

ES29LV160F
Excel Semiconductor Inc.
hardware reset during the chip erase operation immediately terminates the operation. The Chip
Erase command sequence should be reinitiated once the device has returned to reading array
data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#.
See Write Operation Status on page 33 for information on these status bits. When the Embedded
Erase algorithm is complete, the device returns to reading array data and addresses are no longer
latched.
Figure 9.2 on page 31 illustrates the algorithm for the erase operation. See Erase/Program
Operations on page 49 for parameters, and Figure 17.6 on page 50 for timing diagrams.
9.7 Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by
writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are
then followed by the address of the sector to be erased, and the sector erase command. Table
10.1 on page 32 shows the address and data requirements for the sector erase command
sequence.
The device does not require the system to preprogram the memory prior to erase. The Embedded
Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-
out period, additional sector addresses and sector erase commands may be written. Loading the
sector erase buffer may be done in any sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise
the last address and command might not be accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend
during the time-out period resets the device to reading array data. The system must rewrite
the command sequence and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3:
Sector Erase Timer on page 38.) The time-out begins from the rising edge of the final WE# pulse
in the command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. Note that a hardware reset during the sector erase operation immediately
terminates the operation. The Sector Erase command sequence should be reinitiated once the
device has returned to reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by
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