ES29LV160F Datasheet, PDF (13/71 Pages) Excel Semiconductor Inc. – 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

ES29LV160F
Excel Semiconductor Inc.
the erase operation. After the system writes the autoselect command sequence, the device enters
the autoselect mode. The system can then read autoselect codes from the internal register (which
is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode.
Refer to Autoselect Mode on page 17 and Autoselect Command Sequence on page 26 for more
information.
ICC2 in DC Characteristics on page 41 represents the active current specification for the write
mode. AC Characteristics on page 45 contains timing specification tables and timing diagrams for
write operations.
7.4 Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by
reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications
apply. Refer to Write Operation Status on page 33 for more information, and to AC Characteristics
on page 45 for timing diagrams.
7.5 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high
impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V_CC
± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held
at VIH, but not within V_CC ± 0.3 V, the device will be in the standby mode, but the standby current
will be greater. The device requires standard access time (tCE) for read access when the device is
in either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
ICC3 represents the standby current specification shown in the table in DC Characteristics on
page 41.
7.6 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always
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