XRT82L24A Datasheet, PDF (7/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
PIN DESCRIPTIONS
PIN #
NAME
TYPE
DESCRIPTION
5
TxClk_0
21
TxClk_1
55
TxClk_2
71
TxClk_3
I Transmitter_n Clock Input: E1 rate at 2.048MHz ± 50ppm.
During normal operation both in Host Mode and Hardware Mode, TxClk is used
for sampling input data at TxPOS/TData and TxNEG, while MCLK is used as
the timing reference for the transmit pulse shaping circuit. If TxClk is active
while MClk is not present, TxPOS and TxNEG accepts NRZ data input and the
transmit pulse width is determined by TxClk clock duty cycle. If TxClk is tied to
“Low”, TxPOS and TxNEG input accepts RZ data format and the pulse width is
determined by the duty cycle of the input data. In RZ Mode, single-rail data for-
mat is not supported.
In Hardware Mode, if TxClk is tied "High" for more than 10 µs, then TAOS (a
continuous all one's AMI signal) will be transmitted to the line using MCLK as
timing reference.
If TxClk_0 is tied “Low” for more than 10 µs, the transmitter will be powered
down and the output will be tri-stated.
14
TxOFF_0
15
TxOFF_1
16
TxOFF_2
17
TxOFF_3
I Powered-down Transmitter_n:
In Hardware Mode, tie this pin "High" to power-down channel 0 transmitter and
set TTIP_n and TRing_n to high impedance.
NOTE: Internally pulled -up with a 50kΩ resistor.
91
TRing_0
O Transmitter_n Ring Output:
35
TRing_1
Negative Differential data output to the line.
41
TRing_2
85
TRing_3
89
TTIP_0
O Transmitter_n Tip Output:
37
TTIP_1
Positive Differential data output to the line.
39
TTIP_2
87
TTIP_3
MICROPROCESSOR INTERFACE
6
RESET
I Hardware Reset (Active Low). When this pin is tied Low for more than 10µS,
the device is put in the reset state.
NOTE: Internally pulled -up with a 50kΩ resistor.
7
PTS1
I Processor Type Select bit 1:
Host Mode
In Host Mode the appropriate bits are set in the command mode
PTS1 PTS2
0
0
1
0
0
1
1
1
8HC11,8081,80C188 (async.)
Motorola 68K (async.)
Intel x86 (sync.)
Intel i906,Motorola 860 (sync.)
ClkE
I _{Hardware Mode:}
The state of the ClkE input controls the sampling edge of both TxClk and RxClk.
A “1” selects the positive edge of TxClk and RxClk
A “0” selects the negative edge of TxClk and RxClk.
5