XRT82L24A Datasheet, PDF (16/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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FIGURE 8. ANALOG LOCAL LOOP-BACK SIGNAL FLOW JITTER ATTENUATOR SELECTED & IN RECEIVE PATH
TxPOS
TxNEG
TxClk
RxClk
RxPOS
RxNEG
Encoder
Decoder
Timing
Control
Tx
JA
Clock &
Data
Rx
Recovery
TTIP
TRing
RTIP
RRing
FIGURE 9. ANALOG LOCAL LOOP-BACK SIGNAL FLOW JITTER ATTENUATOR SELECTED & IN TRANSMIT PATH
TxPOS
TxNEG
TxClk
RxClk
RxPOS
RxNEG
Encoder
Decoder
JA
Timing
Control
Tx
Clock &
Data
Rx
Recovery
TTIP
TRing
RTIP
RRing
RESET OPERATION
The XRT 82L24A provides both Hardware and Soft-
ware resets. In Hardware reset, with pin 6 forced to
"0" for more than 10µs, the entire state of the device
including the microprocessor R/W registers are reset.
In Software reset, only the state of the interface is re-
set (the microprocessor registers are not affected).
RECEIVER MODES OF OPERATION
Through the microprocessor interface or in Hardware
Mode, XRT 82L24A offers several alternative receive
modes of operation making it flexible for different ap-
plications as dictated by the system requirements.
RECEIVE DATA INVERT MODE
Receive output data by default is active high at Rx-
POS/RDATA and RxNEG/LCV pins. These signals
can be changed to active Low by setting the DATAP
bit in the interface register(Register 1, Bit 3 = “1”). In
single rail mode DATAP = “1”, (Register 0, Bit 7 = “1”),
LCV output also becomes active Low. Data invert
Mode is only available in Host Mode.
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