XRT82L24A Datasheet, PDF (18/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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The choice of these codes is made such that an odd
number of “B” pulses is transmitted between consec-
utive bipolar violation “V” pulses
TRANSMIT PULSE SHAPER
The transmit pulse shaper uses high a speed clock
derived from MCLK to synthesize the shape and
width of the transmitted pulse applied to TTIP and
TRING. The internal high speed timing generator
eliminates the need for a tightly controlled transmit
clock TxClk duty cycle.
The intrinsic jitter at the transmit output using a jitter-
free input clock source and with the jitter attenuator
disabled will generate no more than 0.03UIpp.
DRIVER MONITOR
The driver monitor circuit is used for detecting trans-
mit driver failure by monitoring the activity at TTIP
and TRING. Driver failure may be caused by a short-
circuit in the primary of the transformer or system
problems at the input.
In the Host Mode, when the driver monitor detects no
transitions at TTIP and TRING for more than 128
clock cycles, the DMO bit (bit 7) in the interface regis-
ter is set and results in an interrupt (INT) to be gener-
ated. Driver monitor function is not supported in Hard-
ware Mode.
TxPOS/TDATA and TxNEG Polarity
In HOST Mode, transmit data at TxPOS/TDATA and
TxNEG can be configured for active Low or active
High operation, by controlling the state of the DATAP
bit in the interface register. Writing a "0" to this bit se-
lects active High data and a "1" selects active Low
data. This control bit also selects receive output data
polarity (see Receive Data Invert Mode description).
This feature is not supported in Hardware Mode.
TRANSMIT OFF CONTROL
Each transmit channel of the line interface can be
shut down by writing a "1" to TxOFF in the channel
control interface register. In the “Transmitter off”
mode, the entire transmitter is disabled and the out-
puts at TTIP and TRING are placed in a high imped-
ance state. In Hardware Mode, pins 14 through pin
17 are used for powering down each transmit channel
independently.
INTERFACING THE XRT 82L24A TO THE LINE
The XRT 82L24A in E1 configuration can be trans-
former coupled to 75Ω coaxial or 120Ω twisted pair
lines as shown in Figure 12 and Figure 13 below.
FIGURE 12. XRT 82L24A CHANNEL 1IN AN E1 UNBALANCED 75 Ω APPLICATION
TxPOS
TxNEG
T xL in e C lk
RxPOS
RxNEG
R xL in e C lk
Loss of signal
4
TPOS_0
3
TNEG_0
5
T C lk _0
100
RPOS_0
99
RNEG_0
1
R C lk _ 0
2
RLOS_0
89
TTIP_0
TRing_0 ⁹¹
94
R T IP _0
RRing_0 ⁹⁵
XRT82L24A
R1
9.1Ω
1 ^T1 5
R2
9.1Ω
R3
18.7Ω
4
8
1:2
5 ^T2 1
8
4
1:2
BNC
1
C oaxial
C able
2
BNC
1
C oaxial
C able
2
16