XRT82L24A Datasheet, PDF (33/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

áç
XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
TABLE 15: INTEL INTERFACE TIMING SPECIFICATIONS
SYMBOL
PARAMETER
MIN
t_{64 A8 - A0 Setup Time to ALE_AS}
4
Low
t_{65 A8 - A0 Hold Time from ALE_AS}
2
Low.
Intel Type Read Operation
t_{66 RDS_DS Pulse Width}
260
t_{67 Data Valid from RDS_DS* Low.}
240
t_{68 Data Bus Floating from}
2
RDS_DS* High
t_{69 ALE to RD Time}
4
t_{701 RD Time to "NOT READY" (e.g.,}
RDY_DTCK toggling "Low")
t_{76 Minimum Time between Read}
60
Burst Access (e.g., the rising
edge of RD to falling edge of RD)
Intel Type Write Operations
t_{71 Data Setup Time to WR_R/W}
160
High
t_{72 Data Hold Time from WR_R/W}
0
High
t_{73 High Time between Reads and/}
60
or Writes
t_{74 ALE to WR Time}
4
t_{77 Min Time between Write Burst}
60
Access (e.g., the rising edge of
WR to the falling edge of WR)
t_{770 CS Assertion to falling edge of}
20
WR_R/W
TYP
MAX
145
CONDITION
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
31