XRT82L24A Datasheet, PDF (26/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
áç
REGISTER
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
TABLE 9: MICROPROCESSOR REGISTER MAP
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Command Control Registers (Read/Write)
SR/DR RZData RCLKE TCLKE DATAP CODES IMASK
Reserved Reserved FIFOS
(Set to 0) (Set to 0)
RXJA
TXJA RXMUTE EXLOS
reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0
Channel 0 Register
DMO0
LOS0
LCV0 TCLK0 DMO0IS LOS0IS LVC0IS
Reserved Reserved Reserved Reserved MDMO0 MLOS0 MLCV0
Reserved Reserved Reserved ALOOP0 DLOOP0 RLOOP0 TAOS0
reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0
Channel 1 Register
DMO1
LOS1
LCV1 TCLK1 DMO1IS LLOSIS1 LCV1
Reserved Reserved Reserved Reserved MDMO1 MLOS1 MLCV1
Reserved Reserved Reserved ALOOP1 DLOOP1 RLOOP1 TAOS1
reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0
Channel 2 Register
DMO2
LOS2
LVC2 TCLK2 DMO2IS LLOS2IS LCV2
Reserved Reserved Reserved Reserved MDMO2 MLOS2 MLCV2
Reserved Reserved Reserved ALOOP2 DLOOP2 RLOOP2 TAOS2
reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0
Channel 3 Register
DMO3
LOS3
LCV3 TCLK3 DMO3IS LLOS3IS LCV3
Reserved Reserved Reserved Reserved MDMO3 MLOS3 MLCV3
Reserved Reserved Reserved ALOOP3 DLOOP3 RLOOP3 TAOS3
reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0
SRESET
ICT
reset=0
TCKL0IS
MTCKL0
TxOFF0
reset=0
TCKL1IS
MTCKL1
TxOFF1
reset=0
TCKL2IS
MTCKL2
TxOFF2
reset=0
TCKL3IS
MTCKL3
TxOFF3
reset=0
NOTE: Address 1110 and 1111 R/W Registers (14 and 15)
are Reserved for Exar Testing Purposes
24