XRT82L24A Datasheet, PDF (32/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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Microprocessor Interface I/0 Timing
Intel Interface Timing
The signals used for the Intel microprocessor inter-
face are: Address Latch Enable (ALE), Read Enable
(RD), Write Enable (WR), Chip Select (CS), Address
and Data bits. The microprocessor interface uses
FIGURE 17. INTEL INTERFACE TIMING (READ)
minimum external glue logic and is compatible with
the timings of the 8051 or 80C188 with an 8-16 MHz
clock frequency, and with the timings of x86 or I960
family or microprocessors. The interface timing
shown in Figure 17 and Figure 18 is described in
Table 15.
ALE_AS
A[8:0]
CS
D[7:0]
RD_DS
WR_R/W
RDY_DTCK
t64
t65
Address of Target Register
t67
Not Valid
t69
t66
t701
t68
Valid
t70
FIGURE 18. INTEL INTERFACE TIMING (WRITE)
ALE_AS
A[8:0]
CS
D[7:0]
RD_DS
WR_R/W
t64
t65
Address of Target Register
t770
t71
t72
Data to be Written
t73
t66
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