XRT82L24A Datasheet, PDF (28/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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TABLE 11: COMMAND CONTROL REGISTER 1
COMMAND CONTROL REGISTER 1
PARALLEL PORT ADDRESS: 0001
BIT NO.
NAME
FUNCTION
7
--
Reserved
Must be set to “0” for proper operation.
6
--
Reserved
Must be set to “0” for proper operation.
5
FIFOS
FIFO Size Select:
Writing a "1" to this bit selects 64 bit FIFO depth.
Write "0" to select 32 bit FIFO depth.
4
RxJA
Receive Jitter Attenuator:
Select: Writing a "1" to this bit selects jitter attenuator in the
receive path.
If bit 3(TxJA) is also set, jitter attenuator is disabled.
3
TxJA
Transmit Jitter Attenuator Select:
Writing a "1" to this bit selects jitter attenuator in the transmit
path. If bit 4(RxJA) is also set, jitter attenuator is disabled.
2
RXMUTE Receive Muting:
Writing a "1" to this bit mutes receive data output to a low state
during LOS condition to prevent data chattering.
1
EXLOS
Extended LOS:
Writing a "1" to this bit extends the number of zeros at the input
to 4096 bits, (approximately 2mS), before LOS is declared.
0
ICT
In-Circuit-Testing:
Writing a "1" to this bit causes all output pins to be in high
impedance mode for in-circuit testing. The software ICT function
is equivalent to connecting pin 20 to ground.
NOTE: Register Type Abrbreviation:
R = Read Only, R/W = Read or Write, RUR = Reset Upon Read
REGISTER
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
VALUE
0
0
0
0
0
0
0
0
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