XRT82L24A Datasheet, PDF (2/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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FIGURE 2. BLOCK DIAGRAM OF THE XRT82L24A T1/E1/J LIU (HARDWARE MODE)
TxClk_n/RZData
TxPOS _n/TDATA_n
TxNEG_n
RxClk_n
RxPOS_n/RDATA_n
RxNEG_n/LCV_n
RxLOS_n
INT
RDY_DTACK
PClk/Codes
PTS1/ClkE
PTS2/SR/DR
Reset
WR_R/W/TxOFF0
ALE_AS/TxOFF2
CS/TxOFF3
RD_DS/TxOFF1
HW/HOST
ICT
One of four channels
HDB3
Encoder
MUX
Tx/Rx Jitter
Attenuator
Tx Timing
Control
Tx Pulse
Shaper
Line
Driver
Driver
Monitor
Enable/
Disable
Remote
LoopBack
Digital
LoopBack
HDB3
Decoder
MUX
Tx/Rx Jitter
Attenuator
LOS
Detect
Clock
Generator
Timing & Data
Recovery
Peak
Detector
& Slicer
Local
Analog
LoopBack
Rx
Equalizer
Test
µP Controler & Hardware Interface
TVDD_n
TTIP_n
TRing_n
TGND_n
MClk
RTIP_n
RRing_n
ADD[0]
ADD[1]
ADD[2]
ADD[3]/RxMute
D[0]/FIFOS
D[1]/LOOPEN_0
D[2]/LOOPEN_1
D[3]/LOOPEN_2
D[4]LOOPEN_3
D[5]/LOOPSEL
D[6]/RxJA
D[7]TxJA
2