XRT82L24A Datasheet, PDF (35/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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FIGURE 21. MICROPROCESSOR INTERFACE TIMING - RESET PULSE WIDTH
t90
Reset
TABLE 16: MOTOROLA INTERFACE TIMING SPECIFICATION
SYMBOL
PARAMETER
MIN
TYP
MAX UNITS
Microprocessor Interface - Motorola Read Operations (see Figure 19)
t₇₈ A3 - A0 Setup Time to falling edge of ALE_AS
5
ns
t₇₉ Rising edge of RD_DS to rising edge of RDY_DTCK delay
0
ns
t₈₀ Rising edge of RDY_DTCK to tri-state of D[7:0]
0
ns
Microprocessor Interface - Motorola Write Operations (see Figure 20)
t₇₈ A3 - A0 Setup Time to falling edge of ALE_AS
5
ns
t₈₁ D[7:0] Setup Time to falling edge of RD_DS
10
ns
t₈₂ Rising edge of RD_DS to rising edge of RDY_DTCK delay
0
ns
Reset pulse width - both Motorola and Intel Operations (see Figure 21)
t₉₀ Reset pulse width
30
ns
33