XRT82L24A Datasheet, PDF (25/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

áç
XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
D[7:0]
ADD[3:0]
PTS1
PTS2
TABLE 8: MICROPROCESSOR INTERFACE SIGNAL
Data Input (Output): 8 bits bi-directional data bus for register access.
Address Input: 4 bit address to select internal register location.
Processor Type Select:
PTS1
0
1
0
1
PTS2
0
0
1
1
8HC11,8081,80C188 (async.)
Motorola 68K (async.)
Intel x86 (sync.)
Intel i906,Motorola 860 (sync.)
PCLK
Process Clock Input: Input clock for synchronous microprocessor operation. Maximum clock speed is
16MHz. This pin is internally pulled up for asynchronous microprocessor operation if no clock is present.
ALE_AS
Address Latch Input (Address Strobe): With Intel bus timing, the address inputs are latched into the inter-
nal register on the falling edge of ALE. When configured in Motorola bus timing, the address inputs are
latched into the internal register on the falling edge of AS.
CS
Chip Select Input: This signal must be low in order to access the parallel port.
RD_DS
Read Input (Data Strobe): With Intel bus timing, a low pulse on RD selects a read operation when CS pin
is low. When configured in Motorola bus timing, a low pulse on DS indicates a read or write operation
when CS pin is low.
WR_R/W
Write Input (Read/Write): With Intel bus timing, a low pulse on WR selects a write operation when CS pin
is low. When configured in Motorola bus timing, a high pulse on R/W selects a read operation and a low
pulse on R/W selects a write operation when CS pin is low.
RDY_DTACK Ready Output (Data Transfer Acknowledge Output): With Intel bus timing, RDY is asserted high to indi-
cate the device has completed a read or write operation. When configured in Motorola bus timing, DTACK
is asserted low to indicate the device has completed a read or write operation.
INT
Interrupt Output: This pin is asserted low to indicate an interrupt caused by an alarm condition in the
device status registers. The activation of this pin can be blocked by the interrupt status register bit.
23