XRT82L24A Datasheet, PDF (13/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
consecutive zeros before LOS is declared can be in-
creased to 4096 bits. During extended LOS Mode,
the LOS condition will be cleared when 4096 more
valid data bits are present (when operating in the
Host Mode). The LOS condition is cleared when the
input signal rises above 16dB below 0dB nominal lev-
el and meets 12.5% density of 4 ones in a 32 bit win-
dow with no more than 16 consecutive zeros.
Clock signals generated when LOS is declared
The output signal at the RxClk output pin depends
upon the type of LOS condition that is occurring.
Complete Loss of Signal (Zero Amplitude)
If the XRT 82L24A experiences a complete Loss of
Signal (e.g., no signal amplitude), then the XRT
82L24A Clock Recovery PLL enters the Training
Mode, and Differentially begins to lock onto the signal
applied to the MCLK input pin. As a consequence,
the Clock Recovery PLL will begin to drive a clock
signal to the Terminal Equipment (via the RxClk out-
put pin), which is derived from the MCLK input pin.
Degraded Type of Loss of Signal Event (Non-Zero
Amplitude)
If the XRT 82L24A experiences a degraded type of
LOS event (e.g., where there is still a small amount of
discernible signal amplitude in the line signal, but
small enough to qualify as an LOS event) then the
Clock Recovery PLL could lock onto this degraded
line signal and will subsequently drive the same fre-
quency via the RxClk output pins.
CONDITIONS FOR DECLARING AND CLEARING
LOS IN THE E1 MODE.
Each E1 channel of the XRT 82L24A has two criteria
for LOS Detection, Analog and Digital. A channel
will declare a LOS condition when both of these LOS
Detectors detect an LOS condition.
Analog LOS Detector
The Analog LOS Detector will declare an LOS condi-
tion, if it determines that the amplitude of the incom-
ing line signal has dropped to less than
-15dB (below the nominal pulse amplitude of 3V for
twisted-pair, or 2.37V for coaxial-cable) for at least
32 bit-periods.
The Analog LOS Detector will clear the LOS condi-
tion, if it determines that the incoming line signal is no
more than 12.5dB below the nominal 3V pulse ampli-
tude.
NOTE: The difference in the signal level required to declare
and clear LOS is 2.5dB. This 2.5dB hysteresis is designed
into the Analog LOS Detector circuitry, in order to prevent
chattering in the LOS output pin or bit-field.
Digital LOS Detector
The Digital LOS Detector will declare an LOS condi-
tion, if it detects a string of at least 32 consecutive
"0"s.
The Digital LOS Detector will clear the LOS condition,
if it determines that the incoming E1 line signal has a
pulse density of 12.5% or more without 16 consecu-
tive “0’s” for at least 32 consecutive bit periods.
NOTE: The pulse density requirement of 12.5% accounts
for HDB3 coding.
RECEIVE DATA MUTING
The XRT 82L24A permits the user to “MUTE” the re-
covered data output signals anytime the LOS condi-
tion is declared. If the user invokes this function, then
the RPOS/RDAT and RNEG output pins will be pulled
to GND for the duration that the LOS condition exists.
This feature is useful in that it prevents the LIU from
routing electrical noise (which has been “recovered”
by the Clock Recovery PLL) to the Framer IC and
preventing it from declaring an LOS condition. This
feature is enabled by setting the RXMUTE bit to a “1”
in the Host Mode (Register 1, Bit 2 Location) or by
connecting pin 67 High in the Hardware Mode.
LOOP-BACK MODES
Each channel within the XRT 82L24A can be config-
ured to operate in any of the following loop-back
modes:
• Remote Loop-Back Mode
• Digital Local Loop-Back Mode
• Analog Local Loop-Back Mode
Each of these loop-back modes are described in
some detail below.
REMOTE LOOP-BACK (RLOOP) MODE
With Remote Loop-Back activated, (Channel Control
Register bit 2 = “1”) in Host Mode or in Hardware
Mode with LoopSEL (pin 58) tied Low and LoopEN
tied High received data after the jitter attenuator (if
selected) is looped back to the transmit path using
RxClk as transmit timing. In this mode the data/sig-
nals applied to the TxClk, TPOS/TDAT and TNEG in-
put pins are ignored, while RxClk and received data
will continue to be available at their respective output
pins. Simultaneously setting RLOOP and ALOOP ac-
tive is not allowed (see Loop-Back Mode in Figure 4 &
Figure 5). Remote loop-back has priority over TAOS.
DIGITAL LOCAL LOOP-BACK (DLOOP) MODE
The Digital Local Loop-Back mode allows the trans-
mit clock and data to be looped back to the corre-
sponding receiver output pins through the encoder/
decoder and the jitter attenuator. In this mode, the re-
ceive line signal is ignored, but the transmit data will
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