XRT82L24A Datasheet, PDF (24/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
áç
FIGURE 15. TRANSMIT CLOCK AND INPUT DATA TIMING
TxCLK
T_CLKP
T_CLKR
T_CLKF
TxPOS/TDATA
or
TxNEG
T_SU
T_HO
Data can be active
high or active low.
Note: Set TCLKE bit-4 "High" in Command Control Register 0 to select TxCLK inversion.
FIGURE 16. RECEIVE CLOCK AND OUTPUT DATA TIMING.
R_DY
R_CLKR
R_CLKF
RxCLK
RxPOS
or
RxNEG
R_SU
R_HO
Data can be active
high or active low.
Note: Set RCLKE bit=5 "High"in Command Control Register 0 to select RxCLK inversion.
MICROPROCESSOR INTERFACE
XRT 82L24A is equipped with a microprocessor inter-
face for easy device configuration. The parallel port of
the XRT 82L24A is compatible with both Intel and
Motorola address and data buses.
The device has 4-bit address ADD[3:0] input and 8-bit
bi-directional data bus ADD[7:0]. The signals required
for a generic microprocessor to access the internal
registers are described in Table 8.
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