XRT82L24A Datasheet, PDF (30/39 Pages) Exar Corporation – QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
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TABLE 13: CHANNEL MASK REGISTER
CHANNEL MASK REGISTER
PARALLEL PORT ADDRESS CHANNEL 0: 0011
PARALLEL PORT ADDRESS CHANNEL 1: 0110
PARALLEL PORT ADDRESS CHANNEL 2: 1001
PARALLEL PORT ADDRESS CHANNEL 3: 1100
BIT NO.
NAME
FUNCTION
REGISTER TYPE
7
--
This bit is Reserved.
R/W
6
--
This bit is Reserved.
R/W
5
--
This bit is Reserved.
R/W
4
--
This bit is Reserved.
R/W
3
DMOnIS Driver Monitor Output Interrupt Status:
R/W
Writing a "1" to this bit enables DMO alarm interrupt gener-
ation.
2
LOSnIS Loss of Signal Interrupt Status:
R/W
Writing a "1" to this bit enables LOS alarm interrupt gener-
ation.
1
LCVnIS Line Code Violation Interrupt Status:
R/W
Writing a "1" to this bit enables LCV interrupt generation.
0
TCKLnIS Transmit Clock Loss Interrupt Status:
R/W
Writing a "1" to this bit enables TxClk clock loss interrupt
generation.
NOTE: n = channel number 0 to 3.
NOTE: Register Type Abrbreviation:
R = Read Only, R/W = Read or Write, RUR = Reset Upon Read
RESET VALUE
0
0
0
0
0
0
0
0
28