LM3S101_0610 Datasheet, PDF (98/300 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Input/Outputs (GPIOs)
8.1 Block Diagram
Figure 8-1. GPIO Module Block Diagram
PA0
PA1
PA2
PA3
PA4
PA5
U0Rx
U0Tx
SSIClk
SSIFss
SSIRx
SSITx
UART0
SSI
8.2
PB0
CCP0
Timer 0
PB1
32KHz
Timer 1
PB2
PB3
PB4
C0-
Analog
PB5
C0o/C1-
Comparators
PB6
C0+
PB7
PC0
TCK/SWCLK
TRST
PC1
TMS/SWDIO
JTAG
PC2
TDI
PC3
TDO/SWO
Functional Description
Important: All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the
exception of the five JTAG pins (PB7 and PC[3:0]. The JTAG pins default to their
JTAG functionality (GPIOAFSEL=1). Asserting a Power-On-Reset (POR) or an
external reset (RST) puts both groups of pins back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-2).
The LM3S101 microcontroller contains three ports and thus three of these physical GPIO blocks.
98
October 5, 2006
Preliminary