LM3S101_0610 Datasheet, PDF (72/300 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Bit/Field
26:23
Name
SYSDIV
Type
R/W
22
USESYSDIV
R/W
21:14
reserved
RO
13
PWRDN
R/W
12
OEN
R/W
11
BYPASS
R/W
Reset
0xF
0
0
1
1
1
Description
System Clock Divisor
Specifies which divisor is used to generate the system clock
from the PLL output (200 MHz).
Binary
Value
0000-
1000
1001
1010
1011
1100
1101
1110
1111
Divisor
(BYPASS=1)
reserved
Frequency
(BYPASS=0)
reserved
/10
20 MHz
/11
18.18 MHz
/12
16.67 MHz
/13
15.38 MHz
/14
14.29 MHz
/15
13.33 MHz
/16
12.5 MHz (default)
When reading the Run-Mode Clock Configuration (RCC)
register (see page 71), the SYSDIV value is MINSYSDIV if
a lower divider was requested and the PLL is being used.
This lower value is allowed to divide a non-PLL source.
Use the system clock divider as the source for the system
clock. The system clock divider is forced to be used when
the PLL is selected as the source.
Reserved bits return an indeterminate value, and should
never be changed.
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value
of 1 powers down the PLL. See Table 6-4 on page 74 for
PLL mode control.
PLL Output Enable
This bit specifies whether the PLL output driver is enabled.
If cleared, the driver transmits the PLL clock to the output.
Otherwise, the PLL clock does not oscillate outside the PLL
module.
Note: Both PWRDN and OEN must be cleared to run the
PLL.
PLL Bypass
Chooses whether the system clock is derived from the PLL
output or the OSC source. If set, the clock that drives the
system is the OSC source. Otherwise, the clock that drives
the system is the PLL output clock divided by the system
divider.
72
October 5, 2006
Preliminary