LM3S101_0610 Datasheet, PDF (136/300 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Timers
9.1
Block Diagram
Figure 9-1. GPTM Module Block Diagram
0x0000 (Down Counter Modes )
Interrupt / Config
TimerA
Interrupt
TimerB
Interrupt
GPTMCFG
GPTMCTL
GPTMIMR
GPTMRIS
GPTMMIS
GPTMICR
TimerA Control
GPTMTAPMR
GPTMTAPR
GPTMTAMATCHR
GPTMTAILR
GPTMTAMR
TimerB Control
GPTMTBPMR
GPTMTBPR
GPTMTBMATCHR
GPTMTBILR
GPTMTBMR
TA Comparator
GPTMAR En
GPTMTBR En
TB Comparator
Clock / Edge
Detect
32KHz
RTC Divider
Clock / Edge
Detect
CCP1
System
Clock
0x0000 (Down Counter Modes )
9.2
9.2.1
Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two
16-bit load/initialization registers and their associated control functions. The exact functionality of
each GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see
page 147), the GPTM TimerA Mode (GPTMTAMR) register (see page 148), and the GPTM
TimerB Mode (GPTMTBMR) register (see page 149). When in one of the 32-bit modes, the timer
can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its
two 16-bit timers configured in any combination of the 16-bit modes.
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all
control registers are cleared and in their default states. Counters TimerA and TimerB are initialized
to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 157) and the GPTM TimerB Interval Load (GPTMTBILR)
register (see page 158). The prescale counters are initialized to 0x00: the GPTM TimerA
Prescale (GPTMTAPR) register (see page 161) and the GPTM TimerB Prescale (GPTMTBPR)
register (see page 162).
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October 5, 2006
Preliminary