LM3S101_0610 Datasheet, PDF (274/300 Pages) List of Unclassifed Manufacturers – Microcontroller

Signal Tables
15 Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register (see page 114).
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins
(PB7 and PC[3:0]) which default to the JTAG functionality.
Table 15-1 shows the pin-to-signal-name mapping, including functional characteristics of the
signals. Table 15-2 lists the signals in alphabetical order by signal name. Table 15-3 groups the
signals by functionality, except for GPIOs. Table 15-4 lists the GPIO pins and their alternate
functionality.
Table 15-1. Signals by Pin Number (Sheet 1 of 2)
Pin
Number
Signal Name
1
PB7
TRST
2
PB6
C0+
3
PB5
C0o
C1–
4
PB4
C0–
5
RST
6
LDO
7
VDD
8
GND
9
OSC0
10
OSC1
11
PA0
U0Rx
12
PA1
U0Tx
13
PA2
SSIClk
Pin
Type
Buffer
Type
Description
I/O
TTL GPIO port B bit 7.
I
TTL JTAG TAP reset input.
I/O
TTL GPIO port B bit 6.
I
Analog Analog comparator 0 positive reference input.
I/O
TTL GPIO port B bit 5.
O
TTL Analog comparator 0 output.
I
Analog Analog comparator 1 negative reference input.
I/O
TTL GPIO port B bit 4.
I
Analog Analog comparator 0 negative reference input.
I
TTL System reset input.
-
Power The low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 μF or greater.
-
Power Positive supply for logic and I/O pins.
-
Power Ground reference for logic and I/O pins.
I
Analog Oscillator crystal input or an external clock reference input.
O Analog Oscillator crystal output.
I/O
TTL GPIO port A bit 0.
I
TTL UART0 receive data input.
I/O
TTL GPIO port A bit 1.
O
TTL UART0 transmit data output.
I/O
TTL GPIO port A bit 2.
I/O
TTL SSI clock reference (input when in slave mode and output in
master mode).
274
October 5, 2006
Preliminary