LM3S101_0610 Datasheet, PDF (57/300 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S101 Data Sheet
Register 4: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features.
Device Capabilities 1 (DC1)
Offset 0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MINSYSDIV
reserved
MPU
reserved
PLL WDT SWO SWD JTAG
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
1
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
Bit/Field
Name
Type
Reset Description
31:16
reserved
RO
0
Reserved bits return an indeterminate value, and should
never be changed.
15:12
MINSYSDIV
RO
0x09
The reset value is hardware-dependent. A value of 0x09
specifies a 20-MHz CPU clock with a PLL divider of 10.
See the RCC register (page 71) for how to change the
system clock divisor using the SYSDIV bit.
11:8
reserved
RO
0
Reserved bits return an indeterminate value, and should
never be changed.
7
MPU
RO
0
This bit indicates whether the Memory Protection Unit
(MPU) in the Cortex-M3 is available. A 0 in this bit indicates
the MPU is not available; a 1 indicates the MPU is
available.
See the ARM® Cortex™-M3 Technical Reference Manual
for details on the MPU.
6:5
reserved
RO
0
Reserved bits return an indeterminate value, and should
never be changed.
4
PLL
RO
1
A 1 in this bit indicates the presence of an implemented
PLL in the device.
3
WDT^a
RO
1
A 1 in this bit indicates a watchdog timer on the device.
2
SWO^a
RO
1
A 1 in this bit indicates the presence of the ARM Serial Wire
Output (SWO) trace port capabilities.
1
SWD^a
RO
1
A 1 in this bit indicates the presence of the ARM Serial Wire
Debug (SWD) capabilities.
0
JTAG^a
RO
1
A 1 in this bit indicates the presence of a JTAG port.
a. These bits mask the Run-Mode Clock Gating Control 0 (RCGC0) register (see page 113), Sleep-Mode Clock Gating Control 0
(SCGC0) register (see page 113), and Deep-Sleep-Mode Clock Gating Control 0 (DCGC0) register (see page 113). Bits that are
not noted are passed as 0.
October 5, 2006
57
Preliminary