LM3S101_0610 Datasheet, PDF (7/300 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S101 Data Sheet
List of Figures
Figure 1-1. Stellaris High-Level Block Diagram ........................................................................................... 21
Figure 1-2. LM3S101 Controller System-Level Block Diagram ................................................................... 26
Figure 2-1. CPU Block Diagram .................................................................................................................. 28
Figure 2-2. TPIU Block Diagram .................................................................................................................. 29
Figure 5-1. JTAG Module Block Diagram .................................................................................................... 36
Figure 5-2. Test Access Port State Machine ............................................................................................... 39
Figure 5-3. IDCODE Register Format.......................................................................................................... 43
Figure 5-4. BYPASS Register Format ......................................................................................................... 43
Figure 5-5. Boundary Scan Register Format ............................................................................................... 44
Figure 6-1. External Circuitry to Extend Reset............................................................................................. 46
Figure 6-2. Main Clock Tree ........................................................................................................................ 49
Figure 7-1. Flash Block Diagram ................................................................................................................. 83
Figure 8-1. GPIO Module Block Diagram .................................................................................................... 98
Figure 8-2. GPIO Port Block Diagram.......................................................................................................... 99
Figure 8-3. GPIODATA Write Example...................................................................................................... 100
Figure 8-4. GPIODATA Read Example ..................................................................................................... 100
Figure 9-1. GPTM Module Block Diagram ................................................................................................. 136
Figure 9-2. 16-Bit Input Edge Count Mode Example ................................................................................. 140
Figure 9-3. 16-Bit Input Edge Time Mode Example................................................................................... 141
Figure 9-4. 16-Bit PWM Mode Example .................................................................................................... 142
Figure 10-1. WDT Module Block Diagram ................................................................................................... 167
Figure 11-1. UART Module Block Diagram.................................................................................................. 191
Figure 11-2. UART Character Frame........................................................................................................... 192
Figure 12-1. SSI Module Block Diagram...................................................................................................... 226
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer).......................................................... 228
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 229
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 230
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 230
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 231
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 231
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 232
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 232
Figure 12-10. MICROWIRE Frame Format (Single Frame)........................................................................... 233
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................................... 234
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements............................ 235
Figure 13-1. Analog Comparator Module Block Diagram ............................................................................ 261
Figure 13-2. Structure of Comparator Unit................................................................................................... 262
Figure 13-3. Comparator Internal Reference Structure ............................................................................... 263
Figure 14-1. Pin Connection Diagram.......................................................................................................... 273
Figure 17-1. Load Conditions....................................................................................................................... 285
Figure 17-2. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 287
Figure 17-3. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 288
Figure 17-4. SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 288
Figure 17-5. JTAG Test Clock Input Timing................................................................................................. 290
Figure 17-6. JTAG Test Access Port (TAP) Timing ..................................................................................... 290
Figure 17-7. JTAG TRST Timing ................................................................................................................. 290
October 5, 2006
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Preliminary