LM3S101_0610 Datasheet, PDF (49/300 Pages) List of Unclassifed Manufacturers – Microcontroller

Figure 6-2. Main Clock Tree
OSC1
OSC2
Main
Osc
1-8 MHz
Internal
Osc
15 MHz
÷4
OSCSRC^a
PLL
(200 MHz
output )
OEN ^a
XTAL^a
PWRDN^a
BYPASS^a
LM3S101 Data Sheet
USESYSDIV^a
SYSDIV^a
System Clock
a. These are bit fields within the Run-Mode Clock Configuration(RCC) register.
6.1.4.2
PLL Frequency Configuration
The user does not have direct control over the PLL frequency, but is required to match the external
crystal used to an internal PLL-Crystal table. This table is used to create the best fit for PLL
parameters to the crystal chosen. Not all crystals result in the PLL operating at exactly 200 MHz,
though the frequency is within ±1%. The result of the lookup is kept in the XTAL to PLL
Translation (PLLCTL) register (see page 75).
Table 6-4 on page 74 describes the available crystal choices and default programming of the
PLLCTL register. The crystal number is written into the XTAL field of the Run-Mode Clock
Configuration (RCC) register (see page 71). Any time the XTAL field changes, a read of the
internal table is performed to get the correct value. Table 6-4 on page 74 describes the available
crystal choices and default programming values.
6.1.4.3
PLL Modes
The PLL has two modes of operation: Normal and Power-Down
„ Normal: The PLL multiplies the input clock reference and drives the output.
„ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the
output.
The modes are programmed using the RCC register fields as shown in Table 6-4 on page 74.
6.1.4.4
PLL Operation
If the PLL configuration is changed, the PLL output is not stable for a period of time (PLL
T_READY=0.5 ms) and during this time, the PLL is not usable as a clock reference.
The PLL is changed by one of the following:
„ Change to the XTAL value in the RCC register (see page 71)—writes of the same value do not
cause a relock.
„ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the T_READY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is
set to 0x1200 (that is, ~600 μs at a 8.192-MHz external oscillator clock). Hardware is provided to
keep the PLL from being used as a system clock until the T_READY condition is met after one of the
October 5, 2006
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Preliminary