LM3S101_0610 Datasheet, PDF (76/300 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100
Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110
Register 21: Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120
These registers control the clock gating logic. Each bit controls a clock enable for a given
interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will
generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that
all functional units are disabled. It is the responsibility of software to enable the ports necessary for
the application. Note that these registers may contain more bits than there are interfaces,
functions, or units to control. This is to assure reasonable code compatibility with other family and
future parts.
RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and
DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration
(RCC) register (see page 71) specifies that the system uses sleep modes.
Run-Mode, Sleep-Mode and Deep-Sleep-Mode Clock Gating Control 0 (RCGC0, SCGC0, and DCGC0)
Offset 0x100, 0x110, 0x120
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WDT SWO SWD JTAG
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Bit/Field
Name
Type
Reset Description
31:4
reserved
RO
0
Reserved bits return an indeterminate value, and should
never be changed.
3
WDT
R/W
0
This bit controls the clock gating for the WDT module. If
set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled.^a
2
SWO
R/W
0
This bit controls the clock gating for the SWO module. If
set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled.^a
1
SWD
R/W
0
This bit controls the clock gating for the SWD module. If
set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled.^a
0
JTAG
R/W
1
This bit controls the clock gating for the JTAG module.
The reset state for this bit is 1. At reset, the unit receives a
clock and functions. Setting this bit to 0 leaves the unit
unclocked and disabled.^a
a. If the unit is unclocked, reads or writes to the unit will generate a bus fault.
76
October 5, 2006
Preliminary