LM3S101_0610 Datasheet, PDF (96/300 Pages) List of Unclassifed Manufacturers – Microcontroller

Internal Memory
Register 9: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear
the interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Offset 0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PMISC AMISC
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W1C R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:2
1
Name
reserved
PMISC
0
AMISC
Type
RO
R/W1C
R/W1C
Reset
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
Programming Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled
because a programming cycle completed and was not
masked. This bit is cleared by writing a 1. The PRIS bit in
the FCRIS register (see page 94) is also cleared when the
PMISC bit is cleared.
Access Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled
because an improper access was attempted and was not
masked. This bit is cleared by writing a 1. The ARIS bit in
the FCRIS register is also cleared when the AMISC bit is
cleared.
96
October 5, 2006
Preliminary