LM3S101_0610 Datasheet, PDF (101/300 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S101 Data Sheet
8.2.4
8.2.5
8.2.6
8.3
Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) register (see
page 113).
When programming interrupts, the interrupts should be masked (GPIOIM set to 0). Writing any
value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious
interrupt if the corresponding bits are enabled.
Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is
enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 114), the pin
state is controlled by its alternate function (that is, the peripheral). Software control corresponds to
GPIO mode, where the GPIODATA register is used to read/write the corresponding pins.
Pad Configuration
The pad configuration registers allow for GPIO pad configuration by software based on the
application requirements. The pad configuration registers include the GPIODR2R, GPIODR4R,
GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers.
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers
as well as the GPIOPCellID0-GPIOPCellID3 registers.
Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting PORTA, PORTB, and PORTC in
the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) default to general-purpose input mode
(GPIODIR and GPIOAFSEL both set to 0). Table 8-1 shows all possible configurations of the
GPIO pads and the control register settings required to achieve them. Table 8-2 shows how a
rising edge interrupt would be configured for pin 2 of a GPIO port.
Table 8-1. GPIO Pad Configuration Examples
Register Bit Value^a
Configuration
Digital Input (GPIO)
Digital Output (GPIO)
Open Drain Input (GPIO)
Open Drain Output (GPIO)
Digital Input (Timer CCP)
Digital Output (Timer PWM)
Digital Input/Output (SSI)
0
0
0
1
?
?
X
X
X
X
0
1
0
1
?
?
?
?
?
?
0
0
1
1
X
X
X
X
X
X
0
1
1
1
X
X
?
?
?
?
1
X
0
1
?
?
X
X
X
X
1
X
0
1
?
?
?
?
?
?
1
X
0
1
?
?
?
?
?
?
October 5, 2006
101
Preliminary