LM3S101_0610 Datasheet, PDF (193/300 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S101 Data Sheet
11.2.3
11.2.4
11.2.5
Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit
FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters
indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in
the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 201) is asserted
as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains
asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is
empty, and the last character has been transmitted from the shift register, including the stop bits.
The UART can indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the U0Rx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 191).
The start bit is valid if U0Rx is still low on the eighth cycle of Baud16, otherwise a false start bit is
detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR)
register (see page 199). If the start bit was valid, successive data bits are sampled on every 16th
cycle of Baud16 (that is, one bit period later) according to the programmed length of the data
characters. The parity bit is then checked if parity mode was enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if U0Rx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 197). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit
data in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 205).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 201) and the
UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun
conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE and RXFF bits)
and the UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt
FIFO Level Select (UARTIFLS) register (see page 208). Both FIFOs can be individually
configured to trigger interrupts at different levels. Available configurations include 1/8, 1/4, 1/2, 3/4
and 7/8. For example, if the 1/4 option is selected for the receive FIFO, the UART generates a
receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger
an interrupt at the 1/2 mark.
Interrupts
The UART can generate interrupts when the following conditions are observed:
„ Overrun Error
„ Break Error
„ Parity Error
„ Framing Error
October 5, 2006
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Preliminary